Jade Bus Probe mod
The Jade bus probe is a capable debug tool, but out of the box it only displays the S-100 bus state. You can stop the bus cycle by putting the machine into a wait state by using the dip switch, but this is a coarse tool. Much better would be a means to single step the instructions, with each click of a switch advancing to the next bus cycle.
that's exactly what this mod does. it's a pretty faithful implementation of the circuit in the compupro technical training guide.
parts needed: 2 x 14 pin sockets, 4 x 7 pin headers, wire wrap wire, solder, and 2 cutler-hammer SF6TCX392 or Electroswitch T8201 switches.
the way this circuit works is straightforward:
XRDY, if high, allows bus cycles to run. keeping 2A-2 low means XRDY stays high. open the switch to pull 2A-2 high. now XRDY is controlled by Q from the 74LS74.
PSYNC sets the 74LS74 Q output high; this sets XRDY low, starting a wait state until Q goes low. since PSYNC is only true during the first phase of a bus cycle, this reset only happens at the start of a bus cycle.
the single step switch toggles the flip-flop made up of the two NAND gates, which clocks a constant low D onto Q. this stops the wait state, allowing the bus cycle to complete. the next rising PSYNC will start the next wait state, and that's it.
on to my construction:
overall, I want all the wiring on the component side, but I relax this where this would pollute the display part of the board. I only put a few wires on the back.
first, the rightmost toggle switch I use to be the start/stop switch.
the 2 purple wires go to traces connected to the toggle switch. the yellow line ties one side of the switch to ground.
next, on the front, you'll see the yellow wire between J + K, connected to P0 of X4. that will light up the Patch 0 LED when the bus is running.
from there, it goes to the bottom left, where we put a 4.7k ohm pullup on the switch. this conditions the line high if the switch is open.
just for grins, I put the 2 outputs from the cross-coupled NAND gates on Patch 1+2. those are the green wires coming from the 74HC00 in the patch area.
The step switch needs each side to be grounded, which is what the blue wires do, and I put a 4.7k ohm pullup on each as well. in the above schematic the little black diamond symbols are pullup resistors.
in the next image, the two blue wires above and between B + C are the cross-coupled NAND date inputs that go to pins 9 and 13 of the 74HCT00.
by cross coupling, I mean the outputs of the NAND gates are routed to one input of the other NAND gate.
pin 11 to pin 10, pin 8 to pin 12.
now we need our NAND gates and Flip-Flop. I put in 2 14 pin sockets and 4 7 pin headers connected to the corresponding pins into the left 2 spare footprints.
on the solder side, I tie each of the socket pins to the headers and make sure power and ground are tied to where the TTL wants them.
A2 has an unused open collector NAND gate, which we will use to drive XRDY.
the yellow wire from the pullup at E4 goes to A2-2.
the yellow wire from the 74LS74 in the top socket, pin 9, the Q output, goes to A2-1, the other NAND input.
the NAND output A2-3 goes to F3-11, the XRDY pin.
the there's a quad NAND gate on the lower patch socket, and the second gate output pin 5 we connect to the 74LS74 preset input, pin 10. inputs to the gate are pin 4, at VCC from pin 14, and PSYNC, which we grab via the long yellow wire exiting the right side from E1-1.
the 74LS74 pin 12 gets a ground from pin 7, and pin 13 gets a VCC from pin 14.
the D flip flop's clock, pin 11, comes from the two cross-coupled NAND gates on pins 11 + 10.
here's hi-res scans of the back and front of the board