The humble ALU
Short paper Abstract
Using a Hardware Description Language (HDL) to describe hardware components, such as adders, can open the door to understanding very intricate details of how hardware components are wired together. Through this understanding there is the potential to begin exploring optimisation in existing hardware designs.Â
Currently, Xilinx's IEEE library makes use of an optimized adder design. Given the many variations of adders, a comparison was done between the library adder and a custom built Carry-Skip Adder (CSA). The focus was on trying to optimize for low area usage and reduced longest-route delay. A successful outcome would potentially result in a lower cost alternative to the current default adder designs incorporated in commercial solutions.
Arithmetic Logic Units (ALU) were used as a control measure with only the addition function being alternated with the two aforementioned adders (IEEE library adder and CSA). Both the standard ALU and custom built ALU were designed to support 8, 16, 32, and 64-bit bus widths. Then the following two criteria were used to compare the different designs; 4-Input LookUp Table (area) utilization and the circuitry's longest-route delay (speed).
One of the limitations of this work is that it only looks at fixed-block size skip logic for the CSA. Further work can be put into testing dynamic block sizes, as well as improving the functionality of the ALU by adding support for multiplication and division arithmetic.