Mahendra Sakare

Other sites:

• https://scholar.google.co.in/citations?user=tNQyN5sAAAAJ&hl=en

• https://www.researchgate.net/profile/Mahendra_Sakare (Yet to update)

• https://in.linkedin.com/in/mahendra-sakare-238134b

Education:

• Doctor of Philosophy (Ph.D.), Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India.

• Master of Technology (M. Tech.), Microelectronics and VLSI, SGSITS Indore, Madhya Pradesh, India.

• Bachelor of Engineering  (B. E.), Electrical Engineering, RGPV Bhopal, Madhya Pradesh, India.

Academic and research experience:

• Assistant Professor Grade-I in the department of Electrical Engineering at Indian Institute of Technology (IIT) Ropar from 21/05/2018 to present.

[Confirmation on  Assistant professor Grade I w.e.f. 01/08/2022 (F. No. 9-330/2028/IITRPR/7929 dated 20/09/2022.)]

• Assistant Professor Grade-II in the department of Electrical Engineering at Indian Institute of Technology (IIT) Ropar w.e.f 21/05/2018 (F. No. 9-330/2018/IITRPR/928 dated: 12/06/2018). 

• Assistant Professor in the department of Electronics and Communication (E&C) Engineering at National Institute of Technology (NIT) Rourkela  from 12/03/2018 to 16/05/2018 (2 months and 4 days).

• Assistant Professor in the department of Electronics and Communication (E&C) Engineering at National Institute of Technology (NIT) Surathkal  from 15/01/2018 to 28/02/2018 (1 month and 15 days).

• Research associate at Indian Institute of Technology Bombay from 21/02/2017 to 18/08/2017 (6 months).

Courses offered: (M - July to December, W - January to May, S - June to July)

For undergraduate:

• Tinkering lab (GE 107):  July - Dec 2018.

• Basic electronics lab (GE 108):  July - Dec 2018, Jan - May 2019,  July - Dec 2019, Jan - May 2020.

• Basic Electronics (GE 108): Jan - May 2019,  July - Dec 2019,  Jan - May 2020.

• Associate instructor in Digital Electronics Lab (EE 204):   July - Dec 2019. 

• Analog circuits (EE 301): July - Dec 2020, July - Dec 2021, July - Dec 2022, June - July 2023, July - Dec 2023, July - Dec 2024.

• Analog circuit lab (EE 302): July - Dec 2021, July - Dec 2022, July - Dec 2023, July - Dec 2024.. 

• Development Engineering Project (CP 301): Jan - May 2022  (coordinator). 

• Capstone Project (CP 302): Jan - May 2022, July - Dec 2023  (coordinator).

• Capstone Project (CP 303):  July - Dec 2024 (coordinator).

• Industrial Internship and Comprehensive Viva (II 301): July - Dec 2023 (coordinator). 

• Additional Internship (II 302): July - Dec 2023 (coordinator). 

For post graduate:

• Broadband communication circuit design (EE 652): Jan-May 2020,  Jan-May 2021,  Jan-May 2022.

• Seminar-I (EE 539): July-Dec 2019 (coordinator), July-Dec 2020 (coordinator), July-Dec 2021 (coordinator), July-Dec 2022,  July-Dec 2023.

• Seminar-II (EE 534): Jan-May 2020 (coordinator), Jan-May 2021 (coordinator), Jan-May 2022 (coordinator),  Jan-May 2024.

• Digital IC Design (EE535):  July-Dec 2023 (Co-instructor).

• Special topics on Microelectronics and VLSI design (EE662): Jan-May 2024 (Coordinator).

• Frequency synthesisers, clock and data recovery circuits (EE663): Jan-May 2024,  Jan-May 2025.

PhD students:

• Puneet Singh (2019-M)

• Mayank Kumar Singh (2019-M, Co-guide: Devarshi Das)

• Sahibia Kaur Vohra (2019-M, Guide: Devarshi Das) Graduated on 16 April 2025.

• Hirensh Mehra (2021-M)

• Upendra Chichhula (2021-M)

• Krishan Mehra (2022-W, Guide: Devarshi Das)

• Rahul Walia (2023-M, Co-guide: Devarshi Das) SERB CRG funded PhD scholar

• Taranveer Kaur (2023-W, Co-guide:  Devarshi Das) - Visvesharaya PhD fellow

• Bhuvanesh M (2024) SMDP C2S funded PhD scholar

MTech students:

In project:

• Akhil Awasthi (July 2020 - May 2021)

• Saptarshi Das (July 2020 - May 2021)

• Jasmeet Kaur (July 2021- Dec 2021)

• Abhishek Nigam (July 2021 - May 2022)

• Satyendra Verma (July 2021 - May 2022)

• Ankur Raj (July 2021 - May 2022)

• Vaishnav Pattali (July 2022 - May 2023)

• Vikas Chouhan (July 2022 - May 2023)

• Manish Kumar Gautam (July 2022 - May 2024)

• Gaurav Agarwal (July 2023 - May 2024)

• Rishabh Saxena (Jan 2025 -  May 2025): A High Speed TSPC Style Based PFD with Improved Deadzone Characteristic (Cosupervised with Dr. Pardeep Duhan).

• Anshul Thakur 2023EEM1016 (Jan 2025 -  May 2025): Design and Implementation of Time to Digital Converter and Digitally Controlled Oscillator.

• Ayanmani Das 2023EEM1017 (July 2024 - May 2025): Design and Analysis of Low Phase Noise Voltage-Controlled Oscillators.

• Peace Panmei 2023EEM1020 (July 2024 - May 2025): An Inductance Capacitance based Voltage Control Oscillator using a multi-turn honeycomb based Inductor.

• Rohit_Gautam 2023EEM1036 (July 2024 - May 2025): Phase Noise Analysis of Ring Oscillator using Time-Domain Jitter.

BTech students:

CP 301 Development Engineering project course: 

• SANGA SAI SRINIVAS (2021)

• SAURABH SANKET (2021)

• VIKRAM SINGH (2021)

• MUKESH KUMAR (2021)

• VISHNU KANT SINGH (2021)

• SAGAR GUPTA (2021)

• SHIVAM GARG (2021)

• TANMAY RAI (2021)

• SUJEET KUMAR (2021)

• RITESH CHAUDHRI (2021)

• TARUN GARG (2021)

• Vedant Sati(2022-W)

• Aman Saini (2022-W)

• Ansaf Ahmad (2022-W) 

• Vishakha Agarwal 2021EEB1221 (2023-W): A Resistor-Assisted Supply Sensitivity Improved Ring Oscillator for Wireline & Wireless Applications

• Ashwini Sahane (2023-W) 

• Lokesh Jassal (2023-W) 

• Bhumika Chaudhari (2023-W) 

• Akarshi Roy (2023-W)  

• Abhinav Vasu  2022eeb1286  (2024-25 Sem II): MATLAB implementation of PLL for atomic clock applications.

• Akshat Bisht 2022EEB115 (2024-25 Sem II): Digital PLL implementation in FPGA.

• Aryan Singh 2022eeb1163 (2024-25 Sem II): PRBS Generator Implementation & IBERT Testing.

• Priyanshi Shisodia 2022eeb1206 (2024-25 Sem II): Learning of Digital design flow (RTL to GDS).

CP 302 Capstone Project:

• KUMMARA POOJITH (2020 - W)

• GARIMA AGARAWAL (2020 - W)

• MADHURESHWAR TYAGI (2020 - W)

• SAURABH SANKET (2020 - W)

• VISHAL (2020 - W)

• SANGA SAI SRINIVAS (2021 - M)

• Vedansh (2022-W) 

• Itte Revanth (2023-W)

• Tushar Gupta 2022eeb1222 (2024-25 Sem II): MATLAB modelling of an Atomic clock.

Internship: 

• SHREYASH ANDHALE (Winter 2020-21)

• SNEHAL HRISHIKESH DHAVALE (Winter 2020-21)

• Siddhant Kaashikar IIIT Una ( Summer 2021)

• Vishal Kumar NIT Delhi (Summer 2021)

• Parthasarathy Seshadri, Thiagarajar College of Engineering, Thiruparamkundram, Madurai (Summer 2022).

• Lavisha Yadav, SGSITS Indore (May-July 2023).

• NANDINI M PANDRAPURKAR, Sharnbasva University Kalaburgi, (May-July 2023).

• RUDRA KUMAR (2021eeb1208), IIT Ropar (May-July 2023).

• Ranit Mishra, Culcutta university, Kolkata (June-July 2023).

Publications:

Journals:

1.  Mahendra Sakare, Pavan Kumar Sadhu and Shalabh Gupta, “Bandwidth enhancement of flip-flops using feedback for high-speed integrated circuits,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 8, pp. 768-772, Aug. 2016 (doi: 10.1109/TCSII.2016.2531098). (Third most downloaded paper of August-2016 of the journal) 

2.  Mahendra Sakare, “A Power and Area Efficient Architecture of a PRBS Generator With Multiple Output” in IEEE Transactions on circuits and systems - part II: Express briefs, vol. 64, no. 8, pp. 927-931, Aug. 2017 (doi: 10.1109/TCSII.2016.2641582). 

3. Puneet Singh, Mayank Kumar Singh, Vinayak Gopal Hande and Mahendra Sakare, "An active inductor employed CML latch for high speed integrated circuits” in Analog Integrated Circuits & Signal Processing (Springer Nature, ALOG), 114, pages 277–286 (2023). https://doi.org/10.1007/s10470-022-02070-7

4. Sahibia Kaur Vohra, Sherin Thomas, Shivdeep, Mahendra Sakare, and Devarshi Mrinal Das, "Full CMOS Circuit Implementation for Brain-Inspired Associative Memory with On-chip Trainable Memristive STDP Synapse," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 7, pp. 993-1003, July 2023, doi: 10.1109/TVLSI.2023.3268173.

5. Mayank Kumar Singh, Puneet Singh, Upendra Chichhula, Hirensh Mehra, Devarshi Mrinal Das, and Mahendra Sakare, "A PRBS Generator using Merged XOR-D flip-flop as Building Blocks,” Circuits, Systems & Signal Processing (Springer, CSSP), 2023. https://doi.org/10.1007/s00034-023-02425-z

6. Sahibia Kaur Vohra, Sherin Thomas, Mahendra Sakare, and Devarshi Mrinal Das, "Circuit Implementation of On-chip Trainable Spiking Neural Network using CMOS Based Memristive STDP Synapses and LIF Neurons", Elsevier/ Science direct - Integration journal, Vol. 95, 102122, ISSN 0167-9260, 2024. https://doi.org/10.1016/j.vlsi.2023.102122.

7. Sahibia Kaur Vohra, Mahendra. Sakare, A. P. James and Devarshi Mrinal Das, "SpiMAM: CMOS Implementation of Bio-Inspired Spiking Multidirectional Associative Memory Featuring In-Situ Learning," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 72, no. 1, pp. 2-13, Jan. 2025, doi: 10.1109/TCSI.2024.3427387. 

Conferences: 

1.  Prakash Singh Thakur, Praveen Vyas, Mahendra Sakare, Yogesh Dolekar, Kapil Rathi and Dushyant Mehra, “A high speed rail to rail micropower comparator”, Proceedings of SPIT-IEEE Colloquium and International Conference, vol. 2, pp. 197-199, Mumbai, India, 4-5th Feb. 2008. 

2.  Mohit Singh, Mahendra Sakare and Shalabh Gupta, “Testing of high-speed DACs using PRBS gener- ation with “Alternate-Bit -Tapping,” proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-6, Grenoble, France, 14-18th March 2011. 

3.  Mahendra Sakare, Mohit Singh, and Shalabh Gupta, “A 4 × 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology.” Proceedings of VLSI Design and Test (VDAT), Springer Berlin Heidelberg, pp. 252-257, Kolkata, India, 1st-4th July 2012. 

4.  Mahendra Sakare and Shalabh Gupta, “A high-speed PRBS generator using flip-flops employing feedback for distributed equalization,” proceeding of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 746-749, Melbourne, Australia, 1st-5th June 2014. 

5.  Pragya Maheshwari, Mahendra Sakare, Suhas Kaushik and Shalabh Gupta, “A 12.5 Gbps 1/5-rate CDR using novel sampler based phase detector incorporating DFE,” proceedings of International Conference on VLSI Design (VLSID), pp. 555-556, Kolkata, India, 3rd-7th Jan. 2016. 

6. Mahendra Sakare, “A quarter-rate 27-1 pseudo-random binary sequence generator using interleaved architecture,” proceedings of International Conference on VLSI Design (VLSID), pp. 196-201, Kolkata, India, 3rd - 7th Jan. 2016. 

7.   Puneet Singh, Mayank Kumar Singh, Vinayak Gopal Hande, and Mahendra Sakare, "Design of a PRBS Generator and a serializer Using Active Inductor Employed CML Latch" published in The IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) 2021 that was hosted on online mode by Michigan State University, in East Lansing, Michigan, USA, from Aug 8-11, 2021. 

8.  Mayank Kumar Singh, Puneet Singh, Devarshi Mrinal Das, and Mahendra Sakare, "A Low Power 8 X 27-1 PRBS Generator Using Exclusive-or Gate Merged D flip-Flops" published in The IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) 2021 that was hosted on online mode by Michigan State University, in East Lansing, Michigan, USA, from Aug 8-11, 2021. 

9.  Sahibia Kaur Vohra, Mahendra Sakare and Devarshi Mrinal Das, "Full CMOS Implementation of Bidirectional Associative Memory Neural Network with Analog Memristive Synapse" published in The IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) 2021 that was hosted on the online mode by Michigan State University, in East Lansing, Michigan, USA, from Aug 8-11, 2021. 

10.  Sahibia Kaur Vohra, Sherin A Thomas, Mahendra Sakare and Devarshi Mrinal Das, "Analytical modeling of a CMOS inter-spike interval decoder for resistive crossbar based brain-inspired computing" published in International Symposium on VLSI Design and Test (VDAT) 2021 that was hosted on the online mode by Sardar Vallabhbhai National Institute of Technology Surat, India, from Sep 16-18, 2021. 

11. Mayank Kumar Singh, Puneet Singh, Devarshi Mrinal Das and Mahendra Sakare, "A Low Power Differential Delay Cell without Cross-Coupled Latch for Ring VCO", presented at the 18th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME 2023) was held in Valencia, Spain, from 18th to 21st June 2023. doi: 10.1109/PRIME58259.2023.10161983. (Received "Gold leaf certificate" Best paper award.)

12. Sahibia Kaur Vohra, Mahendra Sakare and Devarshi Mrinal Das, "Full CMOS Analog Circuit Implementation of Multi-Functional Pavlov Associative Memory using STDP Learning" published in IEEE Women in Technology Conference (IEEE WINTECHCON) 2023 that was held in Bengaluru India, on 21st September 2023. (Received Best paper award.)

13. Mayank Kumar Singh, Manish Kumar Gautam, Puneet Singh, Raja Sekhar Nagulapalli, Devarshi Mrinal Das and Mahendra Sakare, "A Double Cross-Coupled Delay Cell for High-Frequency Differential Ring VCOs" presented in IEEE Asia Pacific Conference On Circuits And Systems (APCCAS) 2023 that was held in Hyderabad India, on 19th-22nd November 2023. doi: 10.1109/APCCAS60141.2023.00013.

14. Sahibia Kaur Vohra, Alex James, Mahendra Sakare, and Devarshi Mrinal Das, "Analysing Mismatch effect of CMOS neurons in Spiking Neural Network with Winner-take-all Mechanisms" published in IEEE Nordic Circuits and Systems Conference (NorCAS) 2023 that was held in Aalborg, Denmark, from 30th October to 1st November 2023.

15. Mayank Kumar Singh, Hirensh Mehra, Taranveer Singh, Rajasekhar Nagulapalli, and Mahendra Sakare, “A 15.4 ppm/0C Improved Current Mode Bandgap with 0.9V Supply in 28nm CMOS”, accepted for oral presentation in International Conference on Integrated Circuits, Communication, and Computing Systems  2024, will be held in Una, Himachal Pradesh on 01-02 June 2024.

16. Hirensh Mehra, Mayank Kumar Singh, Zahid Rashid Sheikh, Rajasekhar Nagulapalli and Mahendra Sakare, "A Noise and Mismatch Improved Charge Pump for PLL in 28nm CMOS Technology," 2024 International Conference on Integrated Circuits, Communication, and Computing Systems (ICIC3S), Una, India, 2024, pp. 1-5, doi: 10.1109/ICIC3S61846.2024.10602954. 

17. Mayank Kumar Singh, Rajasekhar Nagulapalli, Devarshi Mrinal Das, and Mahendra Sakare, “An RC-based Dual Injection locked Delay Cell for High-Frequency Ring VCOs”, 35th Irish Signals and Systems Conference (ISSC), Belfast, United Kingdom, 2024, pp. 1-6, doi: 10.1109/ISSC61953.2024.10603085. (hosted by the School of Computing at  Ulster University.)

18. Puneet Singh, Rahul Walia, Rajasekhar Nagulapalli, and Mahendra Sakare, “A linear improved equalizers for short-channel communication link”, 35th Irish Signals and Systems Conference (ISSC), Belfast, United Kingdom, 2024, pp. 1-6, doi: 10.1109/ISSC61953.2024.10603313. (hosted by the School of Computing at  Ulster University.)

19. Zahid Rashid Sheikh, Taranveer Singh, Hitesh Shrimali, Rajasekhar Nagulapalli, and Mahendra Sakare, "A 5.4mW 12GHz Quadrature VCO using current reusing technique in 28nm CMOS technology",  in the 15th International IEEE Conference on Computing, Communication and Networking Technolgies (ICCCNT), Kamand, India, 2024, pp. 1-5, (hosted by IIT-Mandi, Himachal Pradesh, on 24-28 June 2024), doi: 10.1109/ICCCNT61001.2024.10725575. 

20. Mayank Kumar Singh, M. Bhuvanesh, Rajasekhar Nagulapalli, Devarshi Mrinal Das, and Mahendra Sakare, “A 2.9mW Inverter-Based Quadrature Phase Clock Generator with ±0.29◦ Phase Error”, was presented as a Poster at the IEEE International Symposium on Circuits and Systems, held in London, UK from May 25-28, 2025.  

21. Hirensh Mehra, Mayank Kumar Singh, Rajasekhar Nagulapalli, and Mahendra Sakare, “A Phase Noise Improved Charge Pump for Low Jitter PLL”, was presented at the The Irish Signals & Systems Conference 2025, hosted by Atlantic Technological University, Letterkenny, Ireland from June 09-10, 2025.  

22. Mayank Kumar Singh, Rishabh Saxena, Rajasekhar Nagulapalli, Pardeep Duhan, and Mahendra Sakare, "PG-TSPC: Pulse Generator based TSPC PFD using 13 μW Power, 20 MHz to 5 GHz, with Zero Dead Zone and Improved Blind Zone,'' in Proc. VLSI Design and Test (VDAT), hosted by IIT Ropar in Chandigarh, 7-9 August 2025. 

23. Ayanmani Das, Mayank Kumar Singh, Rajasekhar Nagulapalli, and Mahendra Sakare, "A 2.6 mW, -111.6 dBc/Hz Phase Noise, LC-VCO using Harmonic Control for High Frequency Applications,'' in Proc. VLSI Design and Test (VDAT), hosted by IIT Ropar in Chandigarh, 7-9 August 2025.

24. Mayank Kumar Singh, Rajasekhar Nagulapalli, Devarshi Mrinal Das, and Mahendra Sakare, "A 2.7 GHz, -161.18 dBc/Hz FoM, Auxiliary-Controlled Dual-Differential Delay Cell-based Multi-Phase Four-Stage Ring VCO,'' in Proc. VLSI Design and Test (VDAT), hosted by IIT Ropar in Chandigarh, 7-9 August 2025. 

25. Puneet Singh, Rahul Walia, Rajasekhar Nagulapalli, and Mahendra Sakare, "A Resistorless Active Inductor Based CTLE,'' in Proc. VLSI Design and Test (VDAT), hosted by IIT Ropar in Chandigarh, 7-9 August 2025. 

Poster presentation:

1. Mahendra Sakare and Shalabh Gupta, “A 13-Gb/s Full-Rate 27-1 PRBS Generator in 90-nm CMOS Technology”, International Conference on VLSI Design (VLSID), Mumbai, India, 5-10th Jan. 2014. 

Patents:

Granted: 

1. Mahendra Sakare, Shalabh Gupta, and Sadhu Pavan Kumar, “Method and Apparatus for Improving Clock Rates in High Speed Circuits Using Feedback Based Flip-Flops”, Indian patent application, IPA No.: 44/MUM/2014, filed on: 6th Jan. 2014, granted on 13th Dec 2023, Patent number: 481577. 

2. Mahendra Sakare, “A method for reducing power and area in multi-bit pseudo-random binary sequence generator”, Indian patent application, IPA No.: 4983/MUM/2015, filed on: 31st Dec. 2015, granted on 9th May 2023, Patent number: 431332. 

3. Mahendra Sakare, Shalabh Gupta, and Sadhu Pavan Kumar, “Circuit for improving clock rates in high speed electronic circuits using feedback based flip-flops ”, US patent number: US10044345B2, filed on 06 Jan 2014, granted on 07 August 2018.

4. Mahendra Sakare, Mayank Kumar Singh, Puneet Singh, Devarshi Mrinal Das, and Vinayak Gopal Hande, “Pseudo-random binary sequences (PRBS) generator for performing on-chip testing and a method thereof”, US patent 17/578,526 filed on 19 Jan 2022, granted (US 11,774,496 B2) on 03 Oct 2023.

5. Mahendra Sakare, Puneet Singh, and Mayank Kumar Singh, “A symmetrical differential exclusive XOR gate”, Indian patent application number: 202111059328, filed on 20 December 2021, granted  (Indian patent no. 552519) on 17th October 2024.

6. Mahendra Sakare, Puneet Singh, and Mayank Kumar Singh, "A Circuit facilitating optimisation of data frequency and power consumption and a method thereof", Indian Patent application number: 202311063391, filed on 21st September 2023, granted  (Indian patent no. 555624) on 29th November 2024.

Filing stage: 

1. Mahendra Sakare, Mayank Kumar Singh, Puneet Singh, Devarshi Mrinal Das, and Vinayak Gopal Hande, “Pseudo-random binary sequences (PRBS) generator for performing on-chip testing and a method thereof”, Indian patent application number: 202111012409 (TEMP/E-1/14174/2021-DEL), filed on 23 March 2021.

2. Mahendra Sakare, Mayank Kumar Singh, and Puneet Singh, "Constant slope circuit and method for optimising duty cycle of an electronic device", Indian Patent application number: 202211007271, filed on 11 February 2022 (Not yet published).

3. Mahendra Sakare, Mayank Kumar Singh, and Raja Sekhar Nagulapalli, "Bandgap reference (BGR) circuit for generating BGR voltage and a method thereof", Indian Patent application number: 202311046972, filed on 12th July 2023.

7. Mahendra Sakare, Mayank Kumar Singh, and Raja Sekhar Nagulapalli, "Bandgap reference (BGR) circuit for generating BGR voltage and a method thereof", US Patent application number: 18/373713, filed on 27th September 2023.

8. Mahendra Sakare, Mayank Kumar Singh, Upendra Chhichhula and Raja Sekhar Nagulapalli, " An electronic device and fabrication method thereof", Indian Patent application number: 202311081510, filed on 30th November 2023.

9. Mahendra Sakare, Puneet Singh, Rahul Walia, and Raja Sekhar Nagulapalli, "An equalizer and method of operation thereof" Indian Patent application number: 202311081865, filed on 1st December 2023.

10. Mahendra Sakare, Puneet Singh, and Mayank Kumar Singh, "A Circuit facilitating optimisation of data frequency and power consumption and a method thereof", US Patent application number: 18/393261, filed on 21st December 2023.

11. Mahendra Sakare, Mayank Kumar Singh, Hirensh Mehra and Rajasekhar Nagulapalli, "A single-tank quadrature voltage-controlled oscillator (QVCO) and method of operation thereof", Indian Patent application number: 202411009384, filed on 12th February 2024.

12. Mahendra Sakare, Mayank Kumar Singh, Hirensh Mehra and Rajasekhar Nagulapalli, "A phase frequency detector and its method of operation thereof", Indian Patent application number: 202411016895, filed on 8th March 2024.

13. Puneet Singh, Rahul Walia, Rajasekhar Nagulapalli and Mahendra Sakare, "Equalizer and method of operation thereof", United States patent application number: 18/615,959, filed on 25th March 2024.

14. Mahendra Sakare, Mayank Kumar Singh, Upendra Chhichhula and Raja Sekhar Nagulapalli, "An electronic device and fabrication method thereof", United States patent application number: 18/617,417, filed on 26th March 2024.

15. Mahendra Sakare, Mayank Kumar Singh, Hirensh Mehra and Rajasekhar Nagulapalli, "A resistor-assisted supply sensitivity improved ring oscillator for wireline and wireless applications", Indian patent application number: 202311032692, filed on 25th April 2024.

16. Mahendra Sakare, Zahid Rashid Sheikh, Rajasekhar Nagulapalli and Hitesh Shrimali, "A voltage-controlled oscillator (LC VCO) and Method of operation thereof", Indian patent application number: 202411032951, filed on 25th April 2024.

17. Mahendra Sakare, Mayank Kumar Singh, Hirensh Mehra and Rajasekhar Nagulapalli, "A single-tank quadrature voltage-controlled oscillator (QVCO) and method of operation thereof", United States patent application number: 18/654,954, filed on 3rd May 2024.

18. Mahendra Sakare, Puneet Singh, Rahul Walia, and Rajasekhar Nagulapalli, "A linearity improved equalizers for short-channel communication links", Indian patent application number: 202411043124, filed on 3rd June 2024.

19. Mahendra Sakare, Mayank Kumar Singh, Hirensh Mehra and Rajasekhar Nagulapalli, "A phase frequency detector and its method of operation thereof", US Patent application number: 18/747,995, filed on 19th June 2024.

20. Mahendra Sakare, Mayank Kumar Singh, Puneet Singh, Hirensh Mehra and Rajasekhar Nagulapalli, "An improved ultra-low mismatch pump circuit for serializer/deserializer (SERDES) system", Indian Patent application number: 202411048384, filed on 24th June 2024.

21. Mahendra Sakare, Zahid Rashid Sheikh, Tanveer Kaur, Rajasekhar Nagulapalli and Hitesh Shrimali, "A current reusable quadrature voltage-controlled oscillator (QVCO)", Indian patent application: 202411050692, filed on 02/07/2024.

22. Sahibia Kaur Vohra, Sherin A Thomas, Mahendra Sakare, and Devarshi Mrinal Das, "A neuron circuit and method of operation thereof", Indian Patent application number: 202411054405, filed on 16th July 2024.

23. Mahendra Sakare, Mayank Kumar Singh, Hirensh Mehra, and Rajasekhar Nagulapalli, "An improved current mode bandgap circuit for analog and mixed signal systems", Indian Patent application number: 202411062857, filed on 20th August 2024.

24. Mahendra Sakare, Mayank Kumar Singh, Hirensh Mehra and Rajasekhar Nagulapalli, "A resistor-assisted supply sensitivity improved ring oscillator for wireline and wireless applications", US patent application number: 18/829110, filed on 9th September 2024.

25. Mahendra Sakare, Zahid Rashid Sheikh, Rajasekhar Nagulapalli and Hitesh Shrimali, "A voltage-controlled oscillator (LC VCO) and Method of operation thereof", US patent application number: 18/828782, filed on 9th September 2024.

Book chapter:

1. Mahendra Sakare, Mohit Singh, and Shalabh Gupta, “A 4 × 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology.”, Progress in VLSI Design and Test (VDAT), Part of the Lecture Notes in Computer Science (LNCS) book series, Springer Berlin Heidelberg, vol. 7373, pp. 252-257. 

Projects:

1. ISIRD, IIT Ropar (₹ 7 lakhs). - Completed (2019).

2. ISIRD - Ph II, IIT Ropar (₹ 1.07 cr with Dr. Devrashi Mrinal Das and Dr. Brajesh Rawat). - Completed (2021).

3. CRG, SERB, GoI (₹ 26.1483 lakhs) for three years (27-Jan-22 to 26-Oct-2025) 3 Years 9 Months - Ongoing. 

4. Co-investigator (Dr. Rohit Sharma (PI) and Dr. Devarshi Mrinal Das, IIT Ropar) in SMDP-C2S of MeitY (₹ 285 lakhs with IIT Mandi and NIT Hamirpur) for five years (2023 - 2028) - Ongoing.

Consultancy:

1. Audit of Centre for invention, innovation, incubation and Training (ClllTs), located at l.K. Gujral Punjab Technical University, Kapurthala (Hub) and Jabbowal, Sultanpur Lodhi (Spoke) on 4th Oct. and 6th Oct. 2022 (11.80 Lakhs) with Atharva Poundarik,  Dr. Anupam Agrawal, and Dr. Satyam Agarwal IIT Ropar. - Completed

Invited talks:

• Delivered two expert talks/lectures on online short term course on “VLSI Physical Design Techniques” conducted by National Institute of Technical Technical Teachers Training & Research, Chandigarh, Punjab, India held on 19 June 2020.

• Delivered two expert talks/lectures in AICTE Sponsored Short Term Training Programme on " Mixed Signal and Radio Frequency VLSI Design" on 08 Dec 2020 and 18 Dec 2020, respectively conducted by SGSITS Indore Madhya Pradesh.

• Delivered an expert talk/lecture in online Faculty Development Program under the MOU with AICTE on “Emerging Trends in RF and Energy device and Circuits” on 23rd Feb 2021 conducted by NIT Meghalaya.

• Delivered an expert talk/lecture in online Short-Term Training Program on “Emerging Nanoscale Devices, Circuits and Its Applications” on 12th May 2021 that was organized and sponsored by Department of Electronics and Communication Engineering, Delhi Technological University between May 10-14, 2021.

• Delivered expert talk/lectures in online AICTE training and learning (ATAL) faculty development programme (FDP) on "high performance Analog and Mixed signal VLSI System design"  on 16th Dec 2021 (Full day) and 17th Dec 2021 (one lecture) that was organized by IIT Dharwad and sponsored by All India Council for Technical Education (AICTE) between Dec 13-17, 2021. 

• Delivered an expert talk/lecture in an online short-term course (STC) on  " Advances in Signal Processing and VLSI Technologies"  on 6th May 2022 that was organized by NIT Rourkela and sponsored by SERB GoI between 2-6 May 2022. 

• Delivered two expert talks/lectures for the faculty development program (FDP) on "Artificial Intelligence and Its Application in VLSI"  conducted by the Department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Delhi NCR Campus, Ghaziabad, in association with Electronics and ICT Academy of IIT Roorkee from 8th  to 12th January 2024 on online mode. 

• Delivered one expert talk for India's Techade-Chips for Viksit Bharat at Indian Institute of Information Technology (IIIT) Una on 13th March 2024 on online mode. 

• Delivered one expert talk (Date: 29/05/2024) in on a one-week Faculty Development Program on “Advancement and Challenges in VLSI Design and Nanoscale Devices”  held between May 27-31, 2024 organized by the Department of Electronics and Communication Engineering, Delhi Technological University, Delhi-110042. 

• Delivered one expert talk (Date: 26/09/2024) in Faculty Development Program (FDP)  on “Implementing AI-driven Solutions in Engineering and Technology” held between September 23-28, 2024 organized by SCHOOL OF ENGINEERING & TECHNOLOGY IIMT UNIVERSITY, MEERUT.

Awards and honours:

• Received International travel support (ITS) - DST (File no. SB/ITS/0779/2014-15) in 2014.

Academic/Administrative responsibilities:

• DC member of Sunil Pathania (2017EEZ0005), Saurabh Jaiswal (2019csz0009), Prabuddha sinha (2019csz0008).

• I am one of the faculties who started MTech (Microelectronics and VLSI design) at IIT Ropar.

• Developed Electrical hardware part for Tinkering lab, which was conducted for the first time after revised UG curriculum. Since then, the same equipment is in use. 

• Faculty advisor of the 2020 EE batch, IIT Ropar.

• Departmental representative of Academic Committee for Continuing Education and Outreach Activities (ACCEOA) at IIT Ropar.

• Contributed as web chair in organizing committee in International Conference on Advances in VLSI and Embedded Systems (AVES) 2019 conducted by SVNIT Surat India.

• Departmental member for PMRF Shortlisting Policy and shortlisting for year 2021 and 2022.

• Departmental member of Committee for organizing "Dynamic Website Challenge" for year 2023.

• Served as a reviewer in the 4th EAI International Conference on Cognitive Computing and Cyber-Physical Systems 2023. 

• Electrical Engineering department representative for Visvesvaraya PhD scheme from July 2023.

• Faculty advisor of Jammu & Kasmir cell at IIT Ropar w.e.f. 14 May 2024.

• Faculty member of Anti Ragging Squad (ARS) 2024 of IIT Ropar.

• Member of advisory committee for construction and planning (ACCP) 2024 of IIT Ropar.

• VLSI Microelectronics and VLSI design coordinator Since 2023.

• Faculty advisor of MTech Microelectronics and VLSI design 2024 batch.

• Faculty advisor of BTech Engineering Physics 2025 batch.

Other activities:

• Part of InterIIT staff badminton team, tournament held at IIT Guwahati on December 2018.

• Won first prize in Hindi poem competition held on 24 June 2019 at IIT Ropar.

• Won first prize in Hindi poem competition held on 19 September 2019 at IIT Ropar.

• Won second prize in Hindi poem competition held on 18 October 2019 at IIT Ropar.

https://iitrpr.irins.org/profile/99594#expertise_information_panel

- महेन्द्र साकरे