Publications

Publications

(Google scholar)

Livres et brevet

• • André St-Amand et Marc Boulé, Physique des ondes 3e édition, Presses de l'Université du Québec, ISBN 978-2-7605-4561-8, 2016.

  • Marc Boulé et Zeljko Zilic, Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring. Springer, ISBN 978-1402085857, 2008.

  • Marc Boulé et Zeljko Zilic, Automata Unit, a Tool for Designing Checker Circuitry and a Method of Manufacturing Hardware Circuitry Incorporating Checker Circuitry. Numéro de brevet 8,024,691, États-Unis, 20 septembre 2011.

Thèse et mémoire

• • Marc Boulé, Assertion-Checker Synthesis for Hardware Verification, In-Circuit Debugging and On-Line Monitoring. Thèse de doctorat, Université McGill, Montréal, Québec, Canada, 2008. (Directeur de recherche: Zeljko Zilic)

  • Marc Boulé, An FPGA Move Generator for the Game of Chess. Mémoire de maîtrise, Université McGill, Montréal, Québec, Canada, 2002. (Directeur de recherche: Zeljko Zilic, Co-directeur: Monty Newborn)

Articles dans des revues scientifiques (avec comité de lecture)

• 1. Jason Tong, Marc Boulé et Zeljko Zilic, Test Compaction Techniques for Assertion-Based Test Generation. ACM Transactions on Design Automation of Electronic Systems, 19(1):Article 9 (29 pages), décembre 2013.

  2. Katell Morin-Allory, Marc Boulé, Dominique Borrione et Zeljko Zilic, Validating Assertion Language Rewrite Rules and Semantics with Automated Theorem Provers. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(9):1436-1448, septembre 2010.

  3. Jason Tong, Marc Boulé et Zeljko Zilic, Defining and Providing Coverage for Assertion-Based Dynamic Verification. Journal of Electronic Testing – Special Issue on High-Level Design Validation and Test, 26(2):211-225, avril 2010.

  4. Marc Boulé et Zeljko Zilic, Automata-Based Assertion-Checker Synthesis of PSL Properties. ACM Transactions on Design Automation of Electronic Systems, 13(1):Article 4 (21 pages), janvier 2008.

  5. Marc Boulé, Jean-Samuel Chenard et Zeljko Zilic, Debug Enhancements in Assertion-Checker Generation. IET Computers and Digital Techniques – Special Issue on Silicon Debug and Diagnosis, 1(6):669-677, novembre 2007.

  6. Marc Boulé et Zeljko Zilic, An FPGA Move Generator for the Game of Chess. Journal of the International Computer Games Association (ICGA Journal), 25(2):85–94, juin 2002.

Articles dans des comptes rendus de conférences (avec comité de lecture)

• 1. Jason Tong, Marc Boulé et Zeljko Zilic, Accelerating Assertion Assessment Using GPUs. 2016 IEEE International High Level Design Validation and Test Workshop (HLDVT’16), Santa Cruz, Californie, pages x-x, 2016.

  2. Marc Boulé, The Role of Finite Element Method Software in the Teaching of Electromagnetics. 4th Interdisciplinary Engineering Design Education Conference (IEDEC’14), Santa Clara, Californie, pp. 44–51, mars 2014.

  3. Jason Tong, Marc Boulé et Zeljko Zilic, Efficient Data Encoding for Improving Fault Simulation Performance on GPUs. 4th International symposium on Electronic System Design (ISED’13), Singapore, pp. 138–142, décembre 2013.

  4. Jason Tong, Marc Boulé et Zeljko Zilic, Mu-GSIM: A Mutation Testing Simulator on GPUs. 5th Asia Symposium on Quality Electronic Design (ASQED’13), Penang, Malaisie, pages 302-311, 2013. (Prix du meilleur article)

  5. Jason Tong, Marc Boulé et Zeljko Zilic, Assertion Clustering for Compacted Test Sequence Generation. 13th International Symposium on Quality Electronic Design (ISQED’12), Santa Clara, Californie, pages 694-701, 2012.

  6. Jason Tong, Danny Sarraf, Marc Boulé et Zeljko Zilic, Generating Compact Assertions for Control-Based Logic Signals. 54th IEEE Intl. Midwest Symposium on Circuits and Systems (MWSCAS’11), Seoul, Corée, pages 1-4, 2011.

  7. Jason Tong, Marc Boulé et Zeljko Zilic, Airwolf-TG: A Test Generator for Assertion-Based Dynamic Verification. 2009 IEEE International High Level Design Validation and Test Workshop (HLDVT’09), San Francisco, Californie, pages 106-113, 2009.

  8. Yann Oddos, Marc Boulé, Katell Morin-Allory, Dominique Borrione et Zeljko Zilic, MYGEN: Automata-Based On-Line Test Generator for Assertion-Based Verification. 19th Great Lakes Symposium on VLSI (GLSVLSI’09), Boston, Massachusetts, pages 75-80, 2009.

  9. Katell Morin-Allory, Marc Boulé, Dominique Borrione et Zeljko Zilic, Proving and Disproving Assertion Rewrite Rules with Automated Theorem Provers. 2008 IEEE International High Level Design Validation and Test Workshop (HLDVT’08), Lake Tahoe, Nevada, pages 56-63, 2008.

  10. Marc Boulé et Zeljko Zilic, Assertion Checkers - Enablers of Quality Design. 1st Microsystems and Nanoelectronics Research Conference (MNRC 2008), Ottawa, Ontario, pages 97-100, 2008.

  11. Marc Boulé, Jean-Samuel Chenard et Zeljko Zilic, Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis. 8th International Symposium on Quality Electronic Design (ISQED’07), San Jose, Californie, pages 613–618, 2007.

  12. Marc Boulé et Zeljko Zilic, Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation. 12th Asia and South Pacific Design Automation Conference (ASP-DAC2007), Yokohama, Japon, pages 324–329, 2007.

  13. Marc Boulé et Zeljko Zilic, Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties. 2006 IEEE International High Level Design Validation and Test Workshop (HLDVT’06), Monterey, Californie, pages 69–76, 2006.

  14. Marc Boulé, Jean-Samuel Chenard, et Zeljko Zilic, Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug. 24th IEEE International Conference on Computer Design (ICCD’06), San Jose, Californie, pages 294–299, 2006.

  15. Marc Boulé et Zeljko Zilic, Incorporating Efficient Assertion Checkers into Hardware Emulation. 23rd IEEE International Conference on Computer Design (ICCD’05), San Jose, Californie, pages 221–228, 2005.

  16. Marc Boulé et Zeljko Zilic, An FPGA Based Move Generator for the Game of Chess. 2002 IEEE Custom Integrated Circuits Conference (CICC’02), Orlando, Floride, pages 71–74, 2002.

Présentations et congrès

• 1. Marc Boulé, L'outil MBAC et la synthèse de circuits vérificateurs d’assertions, présentation et collaboration de recherche, Laboratoire TIMA-VDS, Institut National Polytechnique de Grenoble, Grenoble, France, février 2008.

  2. Jean-Samuel Chenard, Stephan Bourduas, Nathaniel Azuelos, Marc Boulé et Zeljko Zilic, Hardware Assertion Checkers in On-Line Detection of Faults in a Hierarchical-Ring Network-On-Chip, affiche, Workshop on Diagnostic Services in Network-on-Chips, DATE Conference 2007, Nice, France, avril 2007.

  3. Marc Boulé et Zeljko Zilic, Incorporating Efficient Assertion Checkers into Hardware Emulation, séminaire ReSMiQ, Montréal, septembre 2005.

  4. Marc Boulé et Zeljko Zilic, Incorporating Efficient Assertion Checkers into Hardware Emulation, affiche, TEXPO 2005, Ottawa, octobre 2005.

  5. Marc Boulé et Zeljko Zilic, FPGA Hardware Acceleration: From Chess Playing to Automated Theorem Proving, présentation et affiche, Micronet 2003, Toronto, septembre 2003.

  6. Marc Boulé et Zeljko Zilic, An FPGA Move Generator for the Game of Chess, affiche et démonstration matérielle, TEXPO 2002, Ottawa, juin 2002.

  7. Marc Boulé, Atanu Chattopadhyay, Man-wah Chiang, Stuart McCracken et Zeljko Zilic, Overview of MCSoC2: A Second Generation Managed Clock System on Chip, affiche et présentation, TEXPO 2001, Ottawa, juin 2001. (Mention honorable).