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We present Top Conference Papers in

ISSCC: International Solid-State Circuits Conference
VLSI: Symposium on VLSI Circuits
CICC: Custom Integrated Circuits Conference
A-SSCC: Asian Solid-State Circuits Conference
ESSCIRC: European Solid-State Circuits Conference

Presented Papers

Journal of Solid-State Circuits: 24 Papers
International Solid-State Circuits Conference: 20 Papers
Symposium on VLSI Circuits: 17 Papers
CICC, A-SSCC, and ESSCIRC: 18 Papers

Recently Presented Papers at Conferences

[A-SSCC23] Y. Kwon, S. Lee, C. Lee, H. Yoon, B. Min, and Y. Chae, "An 11bit 360MS/s Pipelined SAR ADC with Dynamic Negative-C Assisted Residue Amplifier", IEEE Asian Solid-State Circuits Conference (A-SSCC), 2023. [link]
[A-SSCC23] H. Lee, D. Seo, Y. Lee, I. Lee, and Y. Chae, "A 23.9 μW 13.6-bit Period Modulation-Based Capacitance-to-Digital Converter with Dynamic Current Mirror Front-end Achieving Capacitor Range of 1 to 68 pF", IEEE Asian Solid-State Circuits Conference (A-SSCC), 2023. [link]
[A-SSCC23] Y. Na, S. Yun, M.-J. Lee, and Y. Chae, "An 8.5ps Resolution, 2000μm2 Phase-Domain Delta-Sigma TDC for Lidar Applications", IEEE Asian Solid-State Circuits Conference (A-SSCC), 2023. [link]
[VLSI23] H. Han, W. Choi, J. Kim, J. Sung, H.-J. Choi, and Y. Chae, “A Highly-Digital PWM-Based Impedance Monitoring IC with 143.2dB DR and 17.7fFrms Resolution” IEEE Symposium on VLSI Technology and Circuits, 2023. [link]
[VLSI23] M. Jang, W.-H. Yu, C. Lee, M. Hays, P. Wang, N. Vitale, P. Tandon, P. Yan, P.-I. Mak, Y. Chae, E.J. Chichilnisky, B. Murmann, and D. G. Muratore, “A 1024-Channel 268 nW/pixel 36x36 μm2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces” IEEE Symposium on VLSI Technology and Circuits, 2023. [link]
[VLSI23] Y.-C. Lin, C. Park, W. Zhao, N. Sun, Y. Chae, and C.-H. Yang, “A 26.4mW, 18.6MS/s Image Reconstruction Processor for IoT Compressive Sensing” IEEE Symposium on VLSI Technology and Circuits, 2023. [link]
[CICC23] J. Yoon, M. Jang, C. Lee, Y. Lim, and Y. Chae, "A 243μW 97.4dB-DR 50kHz-BW Multi-Rate CT Zoom ADC with Inherent DAC Mismatch Tolerance" IEEE Custom Integrated Circuits Conference (CICC), 2023. [link]
[ISSCC23] B. Park, B. Ahn, H.-S. Choi, J. Jeong, K. Hwang, T. Kim, M.-J. Lee, and Y. Chae, “A 400x200 600fps 117.7dB-DR SPAD X-ray Detector with Seamless Global Shutter and Time-Encoded Extrapolation Counter,” IEEE International Solid-State Circuits Conference (ISSCC), 2023. [link]
[A-SSCC22] D. Moon, S. Lee, T. Kim, W.-Y. Choi, and Y. Chae, "A 6-bit 5.12-GS/s Flash ADC with Track-and-Hold Embedded Dynamic Preamplifier in 28nm CMOS" IEEE Asian Solid-State Circuits Conference (A-SSCC), 2022. [link]
[A-SSCC22] T. Kim, S. Lee, and Y. Chae, "A 103.8-dB DR 25ps-to-35ns Resolution Time-to-Digital Converter with Dynamic Ring Oscillator for LiDAR Applications" IEEE Asian Solid-State Circuits Conference (A-SSCC), 2022. [link]
[VLSI22] H. Yoon, T. Kim, Y. Kwon, and Y. Chae, "A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two Stage Dynamic Amplifier" IEEE Symposium on VLSI Circuits (SOVC), 2022. [link]
[ISSCC22] C. Lee, B. Kim, J. Kim, S. Lee, T. Jeon, W. Choi, S. Yang, J.-H. Ahn, J. Bae, and Y. Chae “A Miniaturized Wireless Neural Implant with Body-Coupled Data Transmission and Power Delivery for Freely Behaving Animals” IEEE International Solid-State Circuits Conference (ISSCC), 2022. [link]
[A-SSCC21] H. Lee, C. Lee, J. Lee, Y. Choi, and Y. Chae, “A 0.033-mm2 21.5-aF Resolution Continuous-Time Delta-Sigma Capacitance-to-Digital Converter with Parasitic Capacitance Immunity Up to 480pF” IEEE Asian Solid-State Circuits Conference (A-SSCC), 2021. [link]
[VLSI21] S. Lee, S. Park, Y. Kim, and Y. Chae, “A 0.6V 86.5dB-DR 40kHz-BW Inverter-Based Continuous-Time Delta-Sigma Modulator with PVT-Robust Body-Biasing Technique” IEEE Symposium on VLSI Circuits (SOVC), 2021. [link]
[VLSI21] Y. Lee, B. Cho, C. Lee, J. Kim, and Y. Chae, “A 47.5nJ Resistor-to-Digital Converter for Detecting BTEX with 0.06ppb Resolution” IEEE Symposium on VLSI Circuits (SOVC), 2021. [link]
[CICC21] Y. Chae, M. Jang, C. Lee, S. Lee, and S. Lee “(Invited Paper) A Negative R-Assisted Amplifier on the Virtual Ground and Its Applications ” IEEE Custom Integrated Circuits Conference (CICC), 2021. [link]
[ISSCC21] W. Choi, J. Angevare, I. Park, K.A.A. Makinwa, and Y. Chae “A 0.9V 28MHz Dual-RC Frequency Reference with 5pJ/Cycle and ±200ppm Inaccuracy from -40°C to 85°C” IEEE International Solid-State Circuits Conference (ISSCC), 2021. ISSCC 2021 Takuo Sugano Award for Outstanding Far-East Paper [link]
[ISSCC21] J. Angevare, Y. Chae, and K.A.A. Makinwa “A Highly-Digital 2210μm2 Resistor-Based Temperature Sensor with a One-Point Trimmed Inaccuracy of ±1.3°C (3σ) in 65-nm CMOS” IEEE International Solid-State Circuits Conference (ISSCC), 2021. [link]
[ASSCC20] B. Park, I. Park, W. Choi, Y. Na, and Y. Chae, “A 40m-Range 90fps CMOS Time-of-Flight Sensor using SPAD and In-Pixel Time-Gated Pulse Counter” IEEE Asian Solid-State Circuits Conference (A-SSCC), 2020. [link]
[VLSI20] W. Zhao, C. Park, I. Park, N. Sun, and Y. Chae, “An Always-On 4x Compressive VGA CMOS Imager with 51pJ/pixel and >32dB PSNR” IEEE Symposium on VLSI Circuits (SOVC), 2020. [link]
[CICC20] S. Park, Y. Kim, W. Choi, Y. Lee, S. Kim, Y. Shin, and Y. Chae, “A DTMOST-based Temperature Sensor With 3σ Inaccuracy of ±0.9°C for Self-Refresh Control in 28nm Mobile DRAM” IEEE Custom Integrated Circuits Conference (CICC), 2020. [link]
[ISSCC20] S. Lee, J. Jeong, T. Kim, C. Park, T. Kim, and Y. Chae, “A 5.2Mpixel 88.4dB-DR 12in CMOS X-ray Detector with 16b Column-Parallel Continuous-Time ΔΣ ADCs” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020. [link]
[ISSCC20] C. Lee, T. Jeon, M. Jang, S. Park, Y. Huh, and Y. Chae, “A 6.5μW 10kHz-BW 80.4dB-SNDR Continuous-Time ΔΣ Modulator with Gm-input and 300mVpp Linear Input Range for Closed-loop Neural Recording” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020. [link]
[ISSCC20] M. Jang, C. Lee, and Y. Chae, “A 134μW 24kHz-BW 103.5dB-DR CT ΔΣ Modulator with Chopped Negative-R and Tri-level FIR DAC” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020. [link]
[ISSCC20] Y. Kim, S. Park, S. Song, S, Lee, M. Jang, C. Lee, and Y. Chae, “A 41μW 16MS/s 99.2dB-SFDR Capacitively Degenerated Dynamic Amplifier with Nonlinear Slope Factor Compensation” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020. [link]