Students
Sangheon Lee
M.S. Candidate
(4th Semester)
leesang@kw.ac.kr
Research Interest
STT-MRAM based Computing-in-Memory Architecture, High Speed Low-Power SRAM
Junseo Lee
M.S. Candidate
(4th Semester)
dlwnstj0873@kw.ac.kr
Research Interest
Dual-Rail Circuit for Low-Voltage and High Speed SRAM
Jihwan Park
M.S. Candidate
(4th Semester)
jjihwan96@kw.ac.kr
Research Interest
Low-Voltage/Low Power Digital Logic Circuit Design
Inseong Jeon
M.S. Candidate
(4th Semester)
inseong96@kw.ac.kr
Research Interest
Machine Learning Based Yield Estimation for VLSI Circuit Design
Seokhun Kim
M.S. Candidate
(3rd Semester)
ksh0219@kw.ac.kr
Research Interest
Bayesian Optimization for SRAM Design
Dongho Kim
M.S. Candidate
(3rd Semester)
piterkim1628@kw.ac.kr
Research Interest
Layout Architecture Automation for SRAM Design
Hongwon Kim
M.S. Candidate
(2nd Semester)
hwkim2527@kw.ac.kr
Research Interest
New Memory Yield Optimization
Jaehyeon Woo
M.S. Candidate
(2nd Semester)
macdung9802@kw.ac.kr
Research Interest
Computing-in-Memory Architecture
Taesung Kim
M.S. Candidate
(2nd Semester)
tskim1027@kw.ac.kr
Research Interest
SRAM based Computing-in-Memory Architecture,
High speed SRAM Circuit Design
Ijun Jang
M.S. Candidate
(1st Semester)
hoewon1999@gmail.com
Research Interest
Bayesian Optimization for SRAM Design
Jisu Kang
M.S. Candidate
(1st Semester)
rkdwltn7721@kw.ac.kr
Research Interest
Computing-in-Memory Architecture
Jaeseung Baik
M.S. Candidate
(1st Semester)
ian532310@gmail.com
Research Interest
Bayesian Optimization for SRAM Design
Gwanwoo Park
M.S. Candidate
(1st Semester)
gwanwoo990620@gmail.com
Research Interest
STT-MRAM Circuit Design
Seongwon Kang
M.S. Candidate
(1st Semester)
kangsw421@kw.ac.kr
Research Interest
Computing-in-Memory Architecture