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Associate Professor

Department of Computer Science,

Graduate School of Information Science and Technology,

The University of Tokyo

Research Interests

• • Computer Architecture

  • Algorithm/Hardware Co-design

  • Machine Learning Acceleration

  • Processor Architecture and Memory System

  • High-level Synthesis Compiler

  • FPGA System

Active Project

• • NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

    • Available at GitHub and PyPI.

  • Veriloggen: Python-based High-level Hardware Development Framework

    • Available at GitHub and PyPI.

  • Pyverilog: Python-based Hardware Design Processing Toolkit for Verilog HDL

    • Available at GitHub and PyPI.

Contact

• • E-mail: shinya_at_is_s_u-tokyo_ac_jp

  • Slideshare: my presentation and tutorial slides

  • GitHub: my public software repository

  • CASYS Lab Web Page