Education

• Ph.D. Student in Electrical & Electronic  Engineering, Yonsei Univ., Seoul, March 2026 - Present

• B.S. in Systems Semiconductor Engineering, Yonsei Univ., Seoul, Feburary 2026, Summa Cum Laude

Publications

• I. Choi, S.-C. Lee  and J.-S. Yang,  "HiLLM: Heterogeneous CPU–GPU Inference for Interactive MoE LLM Serving on Local Systems", IEEE/ACM International Symposium on Microarchitecture (MICRO), 2026

• J. Moon, I. Choi, S.-C. Lee  and J.-S. Yang,  "CAPA: Convertibility-Aware Mixed-Precision Accelerator for Asymmetric GEMM in Weight-Only Quantized LLMs", ACM/IEEE Design Automation Conference (DAC), 2026