Education

• Ph.D. Student in Electrical & Electronic  Engineering, Yonsei Univ., Seoul, March 2023 - Present

• B.S. in Electrical & Electronic Engineering, Yonsei Univ., Seoul, February 2023

Publications

• I. Choi, and J.-S. Yang, "DBC: Drift-aware Binary Code for Drift-tolerant Deep Neural Networks", ACM/IEEE Design Automation Conference (DAC), 2025 

• I. Choi, Y.-S. Yoon and  J.-S. Yang, "Bit-slice Architecture for DNN Acceleration with Slice-level Sparsity Enhancement and Exploitation", IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2025 

• S. Kim, J. Moon, J. Oh, I. Choi and J.-S. Yang, "Survey and Evaluation of Converging Architecture in LLMs based on Footsteps of Operations", IEEE Open Journal of the Computer Society, 2025 

• D.-J. Shin*, I. Choi*, and J.-S. Yang, "ViT-slice: End-to-end Vision Transformer Accelerator with Bit-slice Algorithm", ACM/IEEE Design Automation Conference (DAC), 2024

• I. Choi, J.-Y. Hong, J. Jeon, and J.-S. Yang, “RQ-DNN: Reliable Quantization for Fault-tolerant Deep Neural Network,” ACM/IEEE Design Automation Conference Late Breaking Results (DAC), 2023

• J. Jeon, J.-Y. Hong, S. Kim, I. Choi, and J.-S. Yang, “PIE-DRAM: Postponing IECC to Enhance DRAM performance with access table,” ACM/IEEE Design Automation Conference Late Breaking Results (DAC), 2023

• S.-Y. Lee*, I. Choi* and J.-S. Yang, “Bipolar Vector Classifier for Fault-tolerant Deep Neural Networks,” Proc. of ACM/IEEE Design Automation Conference (DAC), 2022