Yukio Miyasaka

Research Interests

Logic Synthesis, Formal Verification, High Performance Computing, Reconfigurable Architectures

Professional Experience

• Apr. 2026 - current, Postdoc, Institute for Integrated Systems, ETH Zurich.

Education

• Aug. 2020 - Dec. 2025, Ph.D., Department of Electrical Engineering and Computer Sciences, University of California, Berkeley.

• Apr. 2018 - Mar. 2020, Master of Engineering, Department of Electrical Engineering and Information System, University of Tokyo.

• Apr. 2014 - Mar. 2018, Bachelor of Engineering, Department of Information and Communication Engineering, University of Tokyo.

Teaching

• TA for EECS151/251 at University of California, Berkeley in Spring 2023 and Fall 2025

• TA for Analog Circuit Lab at University of Tokyo in Spring 2018 and Spring 2019

• TA for FPGA Lab at University of Tokyo in Fall 2018 and Fall 2019

Internships

• May 2024 - Dec. 2024, Synopsys Inc.

• May 2023 - May 2024, Google X and DeepMind

Publications

Journal

1. Jitendra Kumar, Yukio Miyasaka, Asutosh Srivastava, Masahiro Fujita, "Formal Verification of Integer Multiplier Circuits using Binary Decision Diagrams," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 42, no. 4, pp. 1365-1378, 2023.

2. Mingfei Yu, Yukio Miyasaka, Masahiro Fujita, "Parallel Scheduling Attention Mechanism: Generalization and Optimization," IPSJ Transactions on System LSI Design Methodology, 2022.

3. Yukio Miyasaka, Akihiro Goda, Ashish Mittal, Masahiro Fujita, "Synthesis and Generalization of Parallel Algorithm for Matrix-Vector Multiplication," IPSJ Transactions on System LSI Design Methodology, 2020.

International Conference & Workshop

1. Yukio Miyasaka, Walter Lau Neto, Eleonora Testa, Anika Prasad, Michael Shuster, Reto Zimmermann, Patrick Vuillod, Alan Mishchenko, John Wawrzynek, Luca Amaru, "ML-Inspired Logic Synthesis: Improving Multiplier Circuits," In Proceedings of International Symposium on Machine Learning for CAD (MLCAD), 2025.

2. Yukio Miyasaka, Walter Lau Neto, Eleonora Testa, Anika Prasad, Michael Shuster, Reto Zimmermann, Patrick Vuillod, Alan Mishchenko, John Wawrzynek, Luca Amaru, "ML-Inspired Logic Synthesis: Improving Multiplier Circuits," In Proceedings of International Workshop on Logic & Synthesis (IWLS), 2025.

3. Yukio Miyasaka, Alan Mishchenko, John Wawrzynek, "Scalable Framework for Redundancy Analysis and Logic Optimization," In Proceedings of International Workshop on Logic & Synthesis (IWLS), 2025.

4. Yukio Miyasaka, Alan Mishchenko, John Wawrzynek, Dino Ruić, Xiaoqing Xu, "High-Effort Logic Synthesis with Randomized Transduction," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 2025. PDF 

5. Yukio Miyasaka, Alan Mishchenko, John Wawrzynek, Dino Ruić, Xiaoqing Xu, "Randomized Transduction for High-Effort Logic Synthesis," In Proceedings of International Workshop on Logic & Synthesis (IWLS), 2024.

6. Yukio Miyasaka, Alan Mishchenko, John Wawrzynek, Nicholas J. Fraser, "Synthesis of LUT Networks for Random-Looking Dense Functions with Don’t Cares — Towards Efficient FPGA Implementation of DNN," In Proceedings of International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2024. PDF — Best short paper award

7. Yukio Miyasaka, "Transduction Method for AIG Minimization," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 2024. PDF 

8. Yukio Miyasaka, "Transduction Method for AIG Minimization," In Proceedings of International Workshop on Logic & Synthesis (IWLS), 2023. PDF 

9. Yukio Miyasaka, Alan Mishchenko, John Wawrzynek, Nicholas J. Fraser, "Synthesizing Practical Boolean Functions Using Truth Tables," In Proceedings of International Workshop on Logic & Synthesis (IWLS), 2022. PDF

10. Yukio Miyasaka, Alan Mishchenko, John Wawrzynek, "Constraint-Based Hierarchical Placement for FPGAs," In Proceedings of International Workshop on Logic & Synthesis (IWLS), 2021. PDF

11. Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, "Logic Synthesis for Generalization and Learning Addition," In Proceedings of Design Automation and Test in Europe (DATE), 2021. PDF

12. Shubham Rai, Walter Lau Neto, Yukio Miyasaka, et al., "Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization," In Proceedings of Design Automation and Test in Europe (DATE), 2021.

13. Yukio Miyasaka, Masahiro Fujita, "SAT-based data-flow mapping onto array processor," In Proceedings of International Conference on Very Large Scale Integration (VLSI-SoC), 2020. PDF

14. Yukio Miyasaka, Masahiro Fujita, "Auto-Tuning Framework for BDD Packages," In Proceedings of International Workshop on Logic & Synthesis (IWLS), 2020. PDF

15. Akihiro Goda, Yukio Miyaska, Amir Masoud Gharehbaghi, Masahiro Fujita, "Synthesis and Generalization of Parallel Algorithms Considering Communication Constraints," In Proceedings of International Symposium on Quality Electronic Design (ISQED), 2020.

16. Masahiro Fujita, Yusuke Kimura, Xingming Le, Yukio Miyasaka, Amir Masoud Gharehbaghi, “Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations,” In Proceedings of Design Automation and Test in Europe (DATE), 2020.

17. Yukio Miyasaka, Alan Mishchenko, Masahiro Fujita, "A Simple BDD Package without Variable Reordering and Its Application to Logic Optimization with Permissible Functions," In Proceedings of International Workshop on Logic & Synthesis (IWLS), 2019. PDF

18. Yukio Miyasaka, Ashish Mittal, Masahiro Fujita, "Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel Computing," In Proceedings of International Symposium on Quality Electronic Design (ISQED), 2019. PDF

Book Chapter

1. Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek, "SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays," VLSI-SoC: Design Trends, 2021.

Other Research Activities

Demo

1. Yukio Miyasaka, Zhang Xinpei, Takashi Matsumoto, Masahiro Fujita, "Parallel Algorithm for CNN Inference and Its Automatic Synthesis," University Booth at Design Automation and Test in Europe (DATE), 2020.

2. Tomohiro Maruoka, Yukio Miyasaka, Akihiro Goda, Amir Masoud Gharehbaghi, Masahiro Fujita, "Automatic Synthesis of Algorithms on Multi Chip/FPGA with Communication Constraints," Live Demonstrations at International Symposium on Circuits and Systems (ISCAS), 2019.

3. Tomohiro Maruoka, Yukio Miyasaka, Akihiro Goda, Amir Masoud Gharehbaghi, Masahiro Fujita, "Automatic Synthesis of Algorithms on Multi Chip/FPGA with Communication Constraints," University Booth at Design Automation and Test in Europe (DATE), 2019.

Programming Contest

1. Yukio Miyasaka, Jiun-Hao Chen, "1st place: IWLS 2025 Programming Contest," International Workshop on Logic & Synthesis (IWLS), 2025.

2. Yukio Miyasaka, "2nd place: IWLS 2022 Programming Contest, Synthesis from Truth Tables," International Workshop on Logic & Synthesis (IWLS), 2022.

3. Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Ryogo Koike, Takemaru Kadoi, Masahiro Fujita, "Honorable Mention: 2021 CAD Contest, Functional ECO with Behavioral Change Guidance," International Conference on Computer-Aided Design (ICCAD), 2021.

4. Yukio Miyasaka, Sai Sanjeet, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Ryogo Koike, Takemaru Kadoi, Masahiro Fujita, Bidhu Datta Sahoo, Virendra Singh, John Wawrzynek, "3rd place: IWLS 2021 Programming Contest, ML + LS (Part II)," International Workshop on Logic & Synthesis (IWLS), 2021.

5. Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, "Honorable Mention: 2020 CAD Contest, X-value Equivalence Checking," International Conference on Computer-Aided Design (ICCAD), 2020.

6. Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, "1st place: IWLS 2020 Programming Contest, Machine Learning + Logic Synthesis," International Workshop on Logic & Synthesis (IWLS), 2020.

7. Yukio Miyasaka, Xinpei Zhang, Ryogo Koike, Amir Masoud Gharehbaghi, Masahiro Fujita, "Honorable Mention: 2019 CAD Contest, Logic Regression on High Dimensional Boolean Space," International Conference on Computer-Aided Design (ICCAD), 2019.

8. Binod Kumar, Tomohiro Maruoka, Yukio Miyasaka, Jay Adhaduk, Liu Yuhang, Sudarshan Sharma, Masahiro Fujita, Viendra Singh, Amir Masoud Gharehbaghi, "Honorable Mention: 2018 CAD Contest, Smart EC: Program-Building for Name Mapping," International Conference on Computer-Aided Design (ICCAD), 2018.

9. Yusuke Kimura, Peikun Wang, Yukio Miyasaka, Kentaro Iwata, Xingming Le, Xiaoran Han, Amir Masoud Gharehbaghi, Masahiro Fujita, "Third Place: 2017 CAD Contest, Resource-aware Patch Generation," International Conference on Computer-Aided Design (ICCAD), 2017. 

Skills

Programming Language

• C, C++ (write codes for research projects)

• Python (manage text files and generate graphs)

• Verilog (write a simple pipelined superscalar processor)

• CUDA (use shared memory and atomic operation)

Tool

• ABC (Logic synthesis tool by Berkeley Logic Synthesis and Verification Group)

• Minisat, Glucose (SAT solver)

• z3 (SMT solver)

• CUDD (BDD package by Fabio Somenzi)