I am a Failure Analysis Engineer at Ingrasys (Foxconn Group), onboarded in May 2025 after earning my Master’s degree in Electrical and Computer Engineering from Oregon State University. With over seven years of combined industry and academic experience, I specialize in failure analysis and system-level debugging of high-performance servers, specifically the GB200 and GB300 platforms. In my role, I investigate complex customer-reported issues, perform root cause analysis for L10 defects, resolve RMA cases, and develop internal failure analysis workflows and automated test scripts to improve efficiency and traceability. I work closely with customers and cross-functional teams to address field escalations, identify recurring failure trends, and enhance overall product reliability.

I thrive in fast-paced, multicultural environments where I can combine technical depth with customer engagement. Fluent in Mandarin and professionally proficient in English, I am comfortable collaborating with global teams to deliver reliable and timely solutions. I am passionate about solving complex system-level problems and continuously improving processes to ensure high-quality outcomes for both customers and internal stakeholders.

Ingrasys Technology Inc. USA

Failure Analysis Engineer

May. 2025 - present              San Jose, CA

• Spearhead debug and repair of system-level failures on GB200, GB300, and Vera Rubin NVL72 servers. Specialized in resolving complex issues related to the components, such as BMC, HMC, HPM, DPU, and so on, to ensure system reliability.

• Investigate failing system issues via Linux command line, such as ipmitool, lspci, i2c, and so on, providing root cause findings and resolution plans to both internal engineering and customer engineering teams.

• Collaborate closely with customers and cross-functional teams, including customer Test Engineers and Validation Engineers, to identify recurring system-level issues, implement robust solutions, and continuously enhance product performance and reliability.

• Established and streamlined an internal failure analysis system to support NPI manufacturing, improving traceability, turnaround time, and knowledge sharing.

Momo Fubon Media Tech 

Senior Android Engineer

Jul. 2019 - Sep. 2022              Taipei, Taiwan

• Designed and developed scalable Android applications used by millions of users daily with Kotlin and Java in Android Studio, utilizing MVVM and MVP architectural patterns for modularity and maintainability.

• Integrated RESTful APIs with Retrofit, Kotlin Coroutines, and RxJava to handle data transmission across multiple threads, ensuring non-blocking operations and preventing UI freezing during API responses.

• Designed and implemented local data storage solutions using Jetpack Room, SharedPreferences, and Internal/External Storage to handle diverse local storage scenarios.

• Utilized Dagger Hilt for Dependency Injection to reduce boilerplate code and improve maintainability.

• Secured APIs using HTTPS and SSL, enhancing data security and compliance with industry standards.

• Optimized and debugged WebView with Chrome DevTools, optimizing performance and increasing stability.

• Managed Activity and Fragment lifecycles and implemented Jetpack Navigation to ensure smooth transitions, enhancing user experience and reducing app navigation-related issues by 10%.

• Built and managed a custom CI/CD workflow system with Jenkins, Redmine, and Slack, leveraging problem solving skills to automate build and deployment pipelines. Reduced errors, enhanced team communication with real-time notifications and task tracking, and improved efficiency by 20%.

• Mentored junior developers, accelerating onboarding and enhancing team productivity.

Micro-Star International Inc.

Electrical Hardware Engineer

Apr. 2015 - Feb. 2019           Taipei, Taiwan

• Designed motherboard circuits for Intel platforms (6th to 8th generation, SkyLake-S to CoffeeLake-S), X299 series, and AMD AM4 series, including schematic development and design deployment.

• Ensured product signal integrity and stability throughout the design process.

• Developed module circuits for power solutions, providing internal reference designs and enabling efficient implementation.

• Supervised product lines and collaborated with engineers in the factory in China through technical exchanges to ensure seamless production.

• Diagnosed and resolved hardware issues related to materials and design, delivering effective solutions to enhance product quality and reliability.

Master's in Electrical and Computer Engineering at Oregon State University

Sep. 2023 - Mar. 2025        

Corvallis, OR

Cumulative GPA: 3.79/4.0

Taken Courses: VLSI System Design, Hardware Verification, Computer Architecture, Stochastic Signals and Systems, Machine Learning, Network Theory, Operating Systems (JOS Lab), Cyber Security, Contemporary Energy Applications,  Introduction of Parallel Programming.

Bachelor's in Electrical Engineering at Chang Gung University

Sep. 2009 - Jun. 2013 

Taoyuan, Taiwan 

Project: Real-Time Voting Android App via Android mobile phone Bluetooth.

Machine Learning (GitHub Repository)

Gained proficiency in linear and nonlinear regression/classification, boosting techniques, and neural networks. Acquired expertise in logistic regression, LDA, QDA, model validation, and selection methods using tools like Python, Jupyter Notebook, and Anaconda. Leveraged CUDA for faster training of deep learning models and utilized MATLAB for developing and analyzing statistical models.

Final Project: Developed a CNN to classify plant leaves into 38 classes with 98.43% accuracy using PyTorch.

Operating Systems (JOS Lab)

Completed labs 1 to 4, gaining hands-on experience with OS internals and x86 architecture. Implemented a bootloader to initialize hardware and transfer control to the kernel, designed virtual memory mechanisms with page allocation and translation, and built user environments with system calls and context switching. Enhanced the kernel with preemptive multitasking, including scheduling and the yield system call. 

Introduction of Parallel Programming

Developed proficiency in implementing parallel programs using technologies like OpenMP, CUDA, and MPI. Explored core topics including parallel performance analysis, data decomposition, work sharing, and load balancing. Completed projects on parallel matrix multiplication, optimization of multithreaded applications, and performance evaluation on multi-core and GPU architectures. Analyzed threading models and synchronization methods, culminating in a paper analysis of advanced concurrency techniques.

VLSI System Design (GitHub Repo)

Mastered VLSI and digital design using (System)Verilog, specializing in FPGA design with Xilinx/AMD and open-source toolchains. Developed and tested modules for synchronous and asynchronous entities, implemented AES encryption, DSP-based 32-bit multipliers, and addressed clock domain crossing with asynchronous FIFOs. 

Final project: Designed and implemented a five-stage pipeline microprocessor, integrating IF module, EX module, ALU, SRU, and Data Memory.

Hardware Verification

Devised and evaluated 15+ SVA properties to verify design specifications for a memory controller, achieving nearly 100% coverage through random constrained testing with 20+ covergroups. Constructed Do/Tcl/bash scripts and testbench environments for simulation validation, and maintained a test plan mapping 28 specifications to verification methods like Code Coverage, Functional Coverage, FPV, and Linting.

High-Performance Computer Architecture

Learned advanced computer architecture concepts including instruction-level parallelism (ILP), superscalar processors, and multiprocessor systems. Studied memory hierarchy optimization techniques and solid-state device architectures. Developed an understanding of modern research trends and challenges in high-performance computing.

Final Project: Survey on Computing System Approaches for Efficient LLMs(Large Language Models).