Static Timing Analysis FAQ 2

1. What are combinational and Sequential circuits?

   • Combinational circuits:

These circuits generate outputs based only on the current inputs, without considering previous inputs. They are made up of logic gates and have no memory. Combinational circuits are simpler to design and are used in calculators, multiplexers, and demultiplexers.

1. • Sequential circuits:

These circuits generate outputs based on both the current inputs and the previous state of the circuit. They are made up of logic gates and memory elements, such as flip-flops, latches, and registers. Sequential circuits can be synchronous (clock-driven) or asynchronous. They are used in memory elements, registers, counters, game controllers, and security systems.

2. What is Two Stage Synchronizer?

   • A Two-Stage Synchronizer is a digital circuit commonly used in electronics and VLSI design to transfer signals reliably between two clock domains that are asynchronous or have different clock frequencies. When a signal crosses from one clock domain to another, the receiving flip-flop may sample the signal during a transition, causing it to enter a metastable state (neither 0 nor 1). This metastability can propagate errors through the system. A two-stage synchronizer significantly reduces the probability of metastability by giving the signal additional time to stabilize before being used in the receiving domain. 

• The two flops should be placed as close to each other as possible so there is no combinational delay between the flops. This ensures that entire clock cycle is available for the metastability to resolve. There is a possibility that the input will be settled into a wrong value, and this wrong input will be propagated to the subsequent stages. It is important that the input from one domain stays stable for at least one clock cycle so that the wrong stable data(after a metastability event) is not propagated. The disadvantage in using these synchronizers are the overhead it adds in propagation delay, area and power. Special synchronization flops are available in your libraries which have higher value of MTBF, and is specially designed for reducing the failure rate.

3. What is Mean Time Between Failure (MTBF)?

• Mean Time Between Failures (MTBF) is a reliability metric used in digital electronics (and other engineering domains) to estimate the average time a system, component, or device operates before experiencing a failure. It is expressed in hours and is particularly useful in understanding the reliability of hardware systems. 

• MTBF gives you a measure to determine the reliability of the device with respect to metastability failures. It gives the average time between two failures for the device.

4. What is MultiCycle Path?

• A multicycle path is a timing path where the signal requires more than one clock cycle to propagate from the start point (launch flip-flop) to the endpoint (capture flip-flop). Multicycle paths are intentionally designed when the operation or functionality does not need to complete in a single clock cycle. It is common in designs involving complex computations, slower components, or pipelining.

set_multicycle_path 2 -setup -from [start_point] -to [end_point] 

set_multicycle_path 1 -hold -from [start_point] -to [end_point] 

-setup: Allows the setup check to occur after 2 cycles instead of 1.

-hold:  Adjusts hold checks accordingly to prevent violations.

5. What is False Path?

• A false path is a timing path that does not affect the functional operation of the circuit, meaning its timing need not be analyzed or optimized. False paths often exist due to specific design logic where certain transitions are impossible or irrelevant during normal operation. Multiplexed paths, clock gating and control signals are the common examples of false path.

set_false_path -from [start_point] -to [end_point] 

6. What is the use of clock groups in the spec file?

• Clock groups that are mutually exclusive or asynchronous with each other in a design so that the paths between these clocks are not considered during the timing analysis.

7. How to fix the setup and hold violations?

• Setup:

  • Upsizing,

  • Vt swapping (HVT to LVT)

  • Pushing capture flop (adding delay)

  • Pulling launch flop(reducing delay)

• Hold:

  • Downsizing

  • Vt swapping (LVT to HVT)

  • Pulling capture flop (reducing delay)

  • Pushing launch flop (adding delay)

  • Buffering for net delays

8. What happens if we have setup and hold violations in our design?

• Setup and hold timings are to be met in order to ensure that data launched from one flop is captured properly at another and in accordance to the state machine designed. In other words, no timing violations means that the data launched by one flip-flop at one clock edge is getting captured by another flip-flop at the desired clock edge. If the setup check is violated, data will not be captured properly at the next clock edge. Similarly, if hold check is violated, data intended to get captured at the next edge will get captured at the same edge. Moreover, setup/hold violations can lead to data getting captured within the setup/hold window which can lead to metastability of the capturing flip-flop. So, it is very important to have setup and hold requirements met for all the registers in the design and there should not be any setup/hold violations.

9. What is Time Borrowing?

• The time borrowing technique, which is also called cycle stealing, occurs at a latch. In a latch, one edge of the clock makes the latch transparent, that is, it opens the latch so that output of the latch is the same as the data input; this clock edge is called the opening edge. The second edge of the clock closes the latch, that is, any change on the data input is no longer available at the output of the latch; this clock edge is called the closing edge.

10. What are the inputs to STA?

11. What is Dutycycle?

• A duty cycle is the fraction of one period in which a signal or system is active known as Duty cycle. 

Duty cycle = (Ton/Ton+Toff)*100