Static Timing Analysis FAQ 1

1. What is Static Timing Analysis (STA) and why are we doing it?

• Static Timing Analysis (STA) is a technique used in digital circuit design to verify the timing of a circuit without the need for input vectors. 

2. What is Setup time & Hold time?

   • The minimum time required to stabilize inputs before the active clock edge is known as Setup Time. 

   • The minimum time required to stabilize inputs after the active clock edge is known as Hold Time. 

3. What is Setup Slack & Hold Slack?

   • The Setup Slack condition ensures that the data launched by the launch flip-flop reaches the capture flip-flop within one clock cycle. Additionally, the data must arrive at least one unit of time before it is captured by the capture clock. 

Setup Slack = Required Time - Arrival Time

(Arrival Time ≤ Required Time)

T_launch +T_ck-q +T_comb +T_wire ≤ T_clk – T_su – T_un + T_capture

3. • The Hold Slack condition verifies that the data already present at the input of the capture flip-flop remains stable for a sufficient amount of time after the clock edge captures the data from the previous cycle. 

Hold Slack = Arrival Time-Required Time

(Arrival Time ≥ Required Time)

T_launch +T_ck-q +T_ comb +T_wire ≥ T_h +T_un +T_capture

4. What is Dynamic Timing Analysis (DTA)?

   • DTA specifies the complete behavior, including timing and functionality, of the circuit for a given set of input test vectors. 

5. What is the difference between DTA and STA?

   • DTA:

     • Checks for both timing and functionality

     • Dependent on input data (test vectors)

     • Slower because it also checks the functionality

   • STA:

     • Checks for only timing

     • Independent of data

     • Faster and takes less time

6. What is Skew?

   • The difference between capture flop latency and launch flop latency is known as skew.

   • Different types of skew are:

     • Local Skew

     • Global Skew

     • Useful Skew

7. What's the difference between local, global and useful Skew?

   • Local skew is the difference between the launch and capture flop delay of two communicating flops. 

     • Types:

       1. Positive Skew - Effects hold requirement.

       2. Negative Skew - Effects setup requirement.

   • Global Skew is the difference between a design's maximum and minimum clock delay. 

   • The term "useful skew" refers to the purposeful introduction of skew in a timing channel to satisfy setup or hold requirements. 

     • To meet setup - we add delay in capture path

     • To meet hold - we add delay in launch path

8. What is clock Jitter?

   • Clock jitter refers to the variation of a clock edge from its intended position. 

9. What are On Chip Variations(OCV)?

   • The process and environmental conditions may not be uniform across the different portions of the chip. Due to process variations, identical transistors may not have similar characteristics in different portions of the chip.

   • In the context of On-Chip Variations (OCV), a fixed timing derate factor is applied to the delays of all cells in the design. This approach ensures that if process variations during fabrication impact the delay of any cells, the timing requirements will still be met, preventing the chip from failing post-fabrication. 

   • OCV is particularly relevant for technologies above 90nm. 

   • Fabrication process variations can either increase or decrease the delay of a cell; therefore, it is important to establish both early and late values when determining the derate factor. 

% set_timing_derate -cell_delay-rise -data -early 0.98

% set_timing_derate -cell_delay-rise -data -late 1.21

% set_timing_derate -cell_delay-rise -clock -early 0.95

% set_timing_derate -cell_delay-rise -clock -late 1.16

% set_timing_derate -cell_delay-fall -data -early 0.90

% set_timing_derate -cell_delay-fall -data -late 1.12

% set_timing_derate -cell_delay-fall -clock -early 0.94

% set_timing_derate -cell_delay-fall -clock -late 1.07

10. What are Advanced On Chip Variations(AOCV)?

    • Derating in Advanced On-Chip Variation (AOCV) is applied to each cell according to its distance and path depth inside the timing path. This derating also varies depending on the cell type and the drive strength of the cell.

• Distance is defined by a bounding box that encompasses the net and the cells. 

10. • This methodology is used for technologies at a scale of 40nm and above.

    • Distance is the max net length of clock path

    • Path Depth defines the no. of cells in the clock path.

11. What is Derating factor?

    • Timing derate numbers are ratios used to adjust the delay numbers(increase/decrease) obtained from timing reports. This adjustment reduces the rate of deterioration and minimizes failures that can occur under extreme operating conditions. 

12. What is Common Path Pessimism Removal(CPPR)?

    • Common Path Pessimism Removal (CPPR) is a process that eliminates artificial pessimism between a capture and launch flip-flop pair during timing analysis. It achieves this by identifying the shared clock path between the launch and capture clock paths.

13. What are Parametric On chip Variation (POCV)?

    • In POCV analysis, instead of applying a specific derate factor to a cell, the cell delay is calculated based on the delay variation (σ) of that cell. POCV assumes that the normal delay value of a cell follows a normal distribution curve. 

    • In this method, a nominal delay value (μ) is used to model random variations, rather than relying on the minimum or maximum delay values. 

    • Timing analysis is conducted using this nominal delay value (μ) along with the delay variation (σ).

    •  This approach is typically applied in technologies with a feature size larger than 40nm.

14. What is Clock and their types?

    • The signal which is used to trigger all the sequential elements in the design.

      • Types,

        1. Synchronous

        2. Asynchronous

        3. Exclusive

14. • If two clocks have the same source, a stable phase relationship, and a common base period (which should have a common multiple), then they are synchronous with regard to one another. 

      • Ex: time period of two clocks : 2 and 6, here the common base period is 2.

14. • If there is no set phase relationship or shared base period between two clocks in the design, they are considered asynchronous. 

      • Ex: time period of two clocks : 6 and 7, here there is no common base period.

14. • If there is no communication between two clocks, they are exclusive. 

      • For example, a circuit might multiplex two different clock signals onto a clock line, one a fast clock for normal operation and the other a slow clock for lowpower operation.

      • There is no communication between the two clocks because only one of them is functional at any given time.  

      • It is possible to define a "false path" between these clocks that are mutually exclusive. 

15. What is Virtual Clock?

    • In the current design, a virtual clock lacks an actual source, although it can be used to set input or output delays. 

    • To define virtual clocks for signals that interface to externally clocked devices (other blocks), you can use virtual clock cmd. 

CMD: create_clock –period 10 –name vclk –waveform {0 5}

16. What is Gated Clock and Generated Clock?

    • Clock signals that are managed by gating logic are known as gated clocks. The gating clock's setup and hold checks are handled by the tool. 

    • A generated clock is one that is created from another clock signal by a circuit that is part of the design, such a clock divider. 

      • The create_generated_clock cmd is used to create generated clocks in which you can create frequency divided (-divide_by) or frequency multiplied (-multiply_by) clock.

     Create Clock CMD: create_clock –period 10 –waveform {2 4} [get_ports {C1 CK2}]

Generated Clock CMD: create_generated_clock –name dclk\ –source [get_ports CLK] –divide_by 2 [get_ports FF1/Q]

17. What are Edge detecting Circuits?

    • When the designated edge occurs, the Edge Detector component samples the linked signal and produces a pulse. You can choose to detect one of the following edges: Rising Edge, Falling Edge, or Either Edge. 

    • Rising Edge Detector:

      • The Edge Detector compares the current signal value to the condition of the signal at the last rising clock edge. If the edge type chosen in the customizer is the same as the state change, the det terminal will remain high until the next rising clock edge. This indicates that the pulse generated by an edge may be shorter than one clock cycle but never longer. 

1. • Falling Edge Detector:

18. When we use the command "set_input_delay"?

• The set_input_delay cmd is used to specify the min and max amount of delay from a clock edge to the arrival of a signal at a specified input port.

19. What are Recovery and Removal times?

20. What is Hand Shaking Communication?

• A handshake serves as a synchronization method between communicating mechanisms. In its simplest form, it consists of two mechanisms linked by a pair of connections: one for sending signals and the other for receiving signals.