Automated Washing Machine Control System

Overview:

This project involves the design and implementation of an Automatic Washing Machine Control System using Verilog HDL for a digital design simulation. The goal of this system is to simulate the entire washing cycle process through a state machine-based controller. The design includes several key operations: water filling, detergent dispensing, washing, draining, and spinning, along with monitoring for door status and cycle timeouts.

The system is intended to simulate the behavior of an automatic washing machine, allowing for more efficient operation by automating the processes that a typical washing machine goes through during its cycle.

FSM:

Features and Components:

• State Machine Design: The system operates on a finite state machine (FSM) that controls all the stages of the washing cycle. The design includes six main states:

  • Check Door: Verifies that the door is closed and the machine is ready to start.

  • Fill Water: Fills the machine with water when the water level is low.

  • Add Detergent: Dispenses detergent once the water is filled.

  • Washing Cycle: Activates the motor to agitate the clothes.

  • Drain Water: Drains the used water after washing.

  • Dry Spin: Spins the clothes to remove excess water before the cycle is completed.

• Inputs and Outputs:

  • Inputs: start, door_closed, water_level_decrease, detergent_quantity_decrease, cycle_time_out, drained, spin_time_out

  • Outputs: out (a 3-bit control signal for various machine states such as door lock, water valve control, detergent valve control, motor control, drain control, and cycle completion)

• FSM Logic: The logic of the FSM transitions between states based on inputs like the door status, water level, detergent level, and timeout events. Each state corresponds to specific control signals, allowing the machine to progress through different phases of the wash cycle.

• Reset and Start Conditions:

  • The washing machine can be reset at any time to return to the Check Door state.

  • The Start signal initiates the washing cycle, but only when the door is closed and all initial conditions are met.

Verilog Code:

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: 

// Engineer: 

// Create Date: 12/26/2024 11:51:46 AM

// Design Name: 

// Module Name: 

// Project Name: 

// Target Devices: 

// Tool Versions: 

// Description:

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

/////////////////////////////////////////////////////////////////////////////////

module automatic_washing_machine(clk, reset, door_closed,start,

water_level_decrease,detergent_quantity_decrease,cycle_time_out,

drained,spin_time_out,out );

  input clk, reset,start,door_closed,water_level_decrease,

   detergent_quantity_decrease,cycle_time_out,drained,spin_time_out;

    output reg [2:0]out;

    /* door_lock=        3'b001;

       water_volve_on=   3'b010;

      detergent_volve_on=3'b011;

      motor_on=          3'b100;

      drain_volve_on=    3'b101;

      done=              3'b110;

      */

   reg[2:0] pr_state,nxt_state;

 parameter      check_door =3'b000,

                  fill_water=3'b001,

                    detergent=3'b010,

                        cycle=3'b011,

                    drain_water=3'b100,

                      dry_spin=3'b101;

  /////////////////////////////

  always@(posedge clk)

  if(reset) begin

  pr_state<=check_door;

  out <= 3'b000; 

  end 

  else

  pr_state<=nxt_state;

  ////////////////////////////

  always@(start,door_closed,water_level_decrease,

   detergent_quantity_decrease,cycle_time_out,drained,spin_time_out,pr_state)

   case(pr_state)

check_door: begin

        if(start==1 && door_closed==1)

        begin 

        nxt_state=fill_water;

        out=3'b001;  //door_lock=1

        end

        else

        begin

        nxt_state= check_door;

        out=3'b000;

        end

         end

        fill_water:begin

          if(water_level_decrease==0 && detergent_quantity_decrease ==1)

          begin

          nxt_state=detergent;

         out=3'b000;

         end

         else if(water_level_decrease==0 && detergent_quantity_decrease ==0)

        begin

          nxt_state=cycle;

         out=3'b000;

         end

         else

         begin

          nxt_state=fill_water;

         out=3'b010;   //water_volve_on=1

         end

         end

        detergent:begin

          if(detergent_quantity_decrease ==1)

          begin

          nxt_state=detergent;

          out=3'b011;  //detergent_volve_on=1

          end

          else begin

          nxt_state=cycle;

          out=3'b000;  //detergent_volve_on=0

          end 

          end

        cycle:begin

       if(cycle_time_out==1)

       begin

       nxt_state=drain_water;

          out=3'b000;  

      end

      else 

      begin

       nxt_state=cycle;

          out=3'b100;      //motor_on=1       

      end

      end

      drain_water:begin

            if(water_level_decrease==1)

            begin

            nxt_state=fill_water;

            out=3'b000;

            end

            else if(detergent_quantity_decrease ==1)

            begin 

             nxt_state=detergent;

             out=3'b000;

             end

             else if(drained==1)

             begin

             nxt_state=dry_spin;

             out= 3'b101;   //drain_volve_on=1

             end

            else begin

            nxt_state=drain_water;

             out= 3'b000;

             end 

             end

         dry_spin: begin

        if(spin_time_out==1)

        begin

             nxt_state=check_door;

             out= 3'b110;  //done= 1             

             end

            else begin

            nxt_state=dry_spin;

             out= 3'b000;

             end 

              end            

default: begin 

         nxt_state=check_door; 

         out=3'b000;

         end

        endcase

endmodule

Test Bench:

module testbench();

 // Inputs

    reg clk, reset, start, door_closed, water_level_decrease, detergent_quantity_decrease;

    reg cycle_time_out, drained, spin_time_out;

    // Output

    wire [2:0] out;

    // Instantiate the automatic_washing_machine module

    automatic_washing_machine uut (

        .clk(clk),

        .reset(reset),

        .door_closed(door_closed),

        .start(start),

        .water_level_decrease(water_level_decrease),

        .detergent_quantity_decrease(detergent_quantity_decrease),

        .cycle_time_out(cycle_time_out),

        .drained(drained),

        .spin_time_out(spin_time_out),

        .out(out)

    );

    // Clock generation

    always #5 clk = ~clk; // Generate a clock with a period of 10ns

    // Test stimulus

    initial begin

        // Initialize inputs

        clk = 0;

        reset = 1;

        start = 0;

        door_closed = 0;

        water_level_decrease = 1;

        detergent_quantity_decrease = 1;

        cycle_time_out = 0;

        drained = 0;

        spin_time_out = 0;

        // Apply reset

        #10 reset = 0;

        // Test sequence

        // 1. Start with door closed

        #10 start = 1; door_closed = 1;

        // 2. Simulate water filling process

        #15 water_level_decrease = 0;

        // 3. Simulate detergent valve behavior

        #15 detergent_quantity_decrease = 0;

        // 4. Simulate washing cycle

        #25 cycle_time_out = 1;

        // 5. Simulate drain water process

        #15 drained = 1;

        // 6. Simulate dry spin

        #15 spin_time_out = 1;

        // 7. Observe reset to idle

        #30 reset = 1; // Reset after the cycle completion

        #10 $stop;

    end

// Monitor output

    always @(posedge clk) begin

        $display("Time=%t | State Output=%b | Inputs: start=%b, door_closed=%b, water_level_decrease=%b, detergent_quantity_decrease=%b, cycle_time_out=%b, drained=%b, spin_time_out=%b",

                 $time, out, start, door_closed, water_level_decrease, detergent_quantity_decrease, cycle_time_out, drained, spin_time_out);

    end

Simulation Results:

The design was tested using a Verilog testbench, simulating various washing machine inputs and ensuring that the system responds correctly to the changes in those inputs. The system's behavior was observed in a waveform viewer, showing correct state transitions and output values.

Sample simulation results include:

• Initial State: The machine waits for the door to be closed and the start signal to begin.

• Water Filling: When water level decreases, the machine begins filling with water and checks if detergent is ready.

• Detergent Dispensing: Once the water is filled, the detergent valve is activated if the detergent level is sufficient.

• Washing: The motor starts agitating the clothes until the washing cycle timeout occurs.

• Drainage: After washing, the system drains the water, and once the draining is complete, the system moves to the spin cycle.

• Spin Cycle: Finally, the machine enters the drying phase, and after the spin cycle timeout, the washing cycle is completed, returning the machine to the initial state, ready for the next load.

TCL Console:

Time= 5000 | State Output=000 | Inputs: start=0, door_closed=0, water_level_decrease=1, detergent_quantity_decrease=1, cycle_time_out=0, drained=0, spin_time_out=0

Time= 15000 | State Output=000 | Inputs: start=0, door_closed=0, water_level_decrease=1, detergent_quantity_decrease=1, cycle_time_out=0, drained=0, spin_time_out=0

Time= 25000 | State Output=001 | Inputs: start=1, door_closed=1, water_level_decrease=1, detergent_quantity_decrease=1, cycle_time_out=0, drained=0, spin_time_out=0

Time= 35000 | State Output=000 | Inputs: start=1, door_closed=1, water_level_decrease=0, detergent_quantity_decrease=1, cycle_time_out=0, drained=0, spin_time_out=0

Time= 45000 | State Output=011 | Inputs: start=1, door_closed=1, water_level_decrease=0, detergent_quantity_decrease=1, cycle_time_out=0, drained=0, spin_time_out=0

Time= 55000 | State Output=000 | Inputs: start=1, door_closed=1, water_level_decrease=0, detergent_quantity_decrease=0, cycle_time_out=0, drained=0, spin_time_out=0

Time= 65000 | State Output=100 | Inputs: start=1, door_closed=1, water_level_decrease=0, detergent_quantity_decrease=0, cycle_time_out=0, drained=0, spin_time_out=0

Time= 75000 | State Output=000 | Inputs: start=1, door_closed=1, water_level_decrease=0, detergent_quantity_decrease=0, cycle_time_out=1, drained=0, spin_time_out=0

Time= 85000 | State Output=000 | Inputs: start=1, door_closed=1, water_level_decrease=0, detergent_quantity_decrease=0, cycle_time_out=1, drained=0, spin_time_out=0

Time= 95000 | State Output=101 | Inputs: start=1, door_closed=1, water_level_decrease=0, detergent_quantity_decrease=0, cycle_time_out=1, drained=1, spin_time_out=0

Time= 105000 | State Output=110 | Inputs: start=1, door_closed=1, water_level_decrease=0, detergent_quantity_decrease=0, cycle_time_out=1, drained=1, spin_time_out=1

Time= 115000 | State Output=001 | Inputs: start=1, door_closed=1, water_level_decrease=0, detergent_quantity_decrease=0, cycle_time_out=1, drained=1, spin_time_out=1

Time= 125000 | State Output=000 | Inputs: start=1, door_closed=1, water_level_decrease=0, detergent_quantity_decrease=0, cycle_time_out=1, drained=1, spin_time_out=1

Time= 135000 | State Output=000 | Inputs: start=1, door_closed=1, water_level_decrease=0, detergent_quantity_decrease=0, cycle_time_out=1, drained=1, spin_time_out=1

Breakdown of the States and Output:

• Time = 5000:

  • State Output = 000: This is the initial state, which should be check_door when start = 0 and door_closed = 0. The machine is idle and waiting for the start and door to be closed.

• Time = 15000:

  • State Output = 000: Still in check_door, no change as start = 0 and door_closed = 0.

• Time = 25000:

  • State Output = 001: The machine transitions to fill_water when start = 1 and door_closed = 1. This is expected behavior, with the door lock (3'b001).

• Time = 35000:

  • State Output = 000: The machine should transition to detergent if water_level_decrease = 0 and detergent_quantity_decrease = 1, which seems correct because it's now waiting for detergent after water is filled.

• Time = 45000:

  • State Output = 011: This is correct, as detergent_quantity_decrease = 1 means the detergent valve is on (3'b011).

• Time = 55000:

  • State Output = 000: The transition should happen to cycle when detergent_quantity_decrease = 0. The detergent is now done, and the washing cycle is about to start.

• Time = 65000:

  • State Output = 100: The machine enters the washing cycle, and the motor is on (3'b100), which is correct.

• Time = 75000:

  • State Output = 000: It seems the cycle is still going, but the motor output is off now (3'b000), which likely corresponds to waiting for the cycle_time_out.

• Time = 85000:

  • State Output = 000: No change, and the machine stays in cycle with no motor activity.

• Time = 95000:

  • State Output = 101: The machine transitions to drain_water, as drained = 1. The drain valve is on (3'b101).

• Time = 105000:

  • State Output = 110: After draining, the machine moves to dry_spin and the spin time out occurs (3'b110), signaling that the process is complete.

• Time = 115000:

  • State Output = 001: The cycle appears to be finished and returns to check_door with door lock (3'b001), indicating it's ready for the next cycle.

• Time = 125000 and Time = 135000:

  • State Output = 000: The machine seems idle in check_door after finishing the cycle.

Technologies Used:

• Verilog HDL: Used to describe the hardware design and simulate the washing machine control system.

• FSM (Finite State Machine): The control logic behind the washing machine, governing the transitions between different operational states.

• Testbench Simulation: A Verilog testbench was written to simulate and monitor the behavior of the washing machine, ensuring correct state transitions and output signals.

Project Significance:

This project demonstrates the power of digital design and state machine logic to model and control a real-world application. By automating tasks such as filling water, dispensing detergent, and running cycles, this system reduces the need for manual intervention in a typical washing machine, enhancing the user experience. Furthermore, this project provides a foundational understanding of how embedded control systems can be used to manage complex operations.

Future Enhancements:

• Integration with sensors for automatic detection of water levels, detergent levels, and load size.

• Energy efficiency improvements based on cycle optimization.

• User interface development for better control, including the ability to select wash modes, time settings, etc.

Conclusion:

This Automated Washing Machine Control System is a practical implementation of a digital design project with real-world relevance. By utilizing a finite state machine to manage various washing machine operations, this project demonstrates how embedded systems can enhance everyday devices, contributing to smarter, more efficient home appliances.