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Introduction
Introduction
- Digital baseband
- Source coding, Channel coding, Modulation
- Channel coding
- Used for correcting the transmission errors
- Popular channel codes used in communication systems : Polar codes, LDPC codes
Polar Codes
Polar Codes
- An emerging channel code proposed by Erdal Arikan, Bilkent University, Turkey. It is selected as one of the channel codes in standard of 5G eMBB
- Channels are polarized, i.e., one channel is either especially good or especially bad.
- List successive cancellation decoding
- The most popular decoding scheme of polar codes due to its extraordinary error correction performance
- The large the list size, the better the error correction performance but the higher the complexity
Hardware Architecture of LSCD with Large List Size for Polar Codes
Hardware Architecture of LSCD with Large List Size for Polar Codes
Low-latency Architecture
Low-latency Architecture
- With two newly proposed algorithms
- Double thresholding scheme (DTS)
- Selective expansion
- Achieved spec: 460 Mbps (UMC 90nm) for LSCD with N=1024, L=16
- Both the decoding throughput and the list size are doubled when compared with the state-of-the-art architectures
High-throughput Architecture
High-throughput Architecture
- With two newly proposed algorithms
- Multi-bit DTS
- Partial G-node look-ahead
- Achieved spec: 1103/977/827 Mbps (UMC 90nm) for LSCD with N=1024, L=8/16/32
- The first architecture supports L=32 on ASIC
Reducing Hardware Complexity of the Functional Blocks in Polar Decoders
Reducing Hardware Complexity of the Functional Blocks in Polar Decoders
High Performance Partial-Sum Network (HPPSN)
High Performance Partial-Sum Network (HPPSN)
- A novel folded HPPSN architecture is proposed to seamlessly integrate with the folded PE architecture of the semi-parallel SCD.
- Experimental results show the advantages of the proposed decoding architectures in both performance and area aspects.
List High Performance Partial-Sum Network (LHPPSN)
List High Performance Partial-Sum Network (LHPPSN)
- a high-performance area-efficient partial-sum generation unit is proposed for semi-parallel LSCD
- Experimental results show that the area and delay of the proposed designs are significantly reduced
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