Chen, Xizi, Jingyang Zhu, Jingbo Jiang, and Chi-Ying Tsui. "Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2022).
Chen, Xizi, Jingbo Jiang, Jingyang Zhu, and Chi-Ying Tsui. "SubMac: Exploiting the subword-based computation in RRAM-based CNN accelerator for energy saving and speedup." Integration 69 (2019): 356-368.
Zhu, Jingyang, Zhiliang Qian, and Chi-Ying Tsui. "BiLink: A high performance NoC router architecture using bi-directional link with double data rate." Integration 55 (2016): 30-42.
Qian, Zhi-Liang, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, and Radu Marculescu. "A support vector regression (SVR)-based latency model for network-on-chip (NoC) architectures." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, no. 3 (2015): 471-484.
Qian, Zhiliang, Paul Bogdan, Chi-Ying Tsui, and Radu Marculescu. "Performance evaluation of noc-based multicore systems: From traffic analysis to noc latency modeling." ACM Transactions on Design Automation of Electronic Systems (TODAES) 21, no. 3 (2016): 1-38.
Qian, Zhiliang, Syed Mohsin Abbas, and Chi-Ying Tsui. "Fsnoc: A flit-level speedup scheme for network on-chips using self-reconfigurable bidirectional channels." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, no. 9 (2014): 1854-1867.
Wang, Xiaomeng, Xuejiao Liu, Xianghong Hu, Xiaopeng Zhong, Xizi Chen, Yu Liu, Patrick Kong, Fengshi Tian, and Chiying Tsui. "TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W supporting Multibit Matrix-Vector Multiplication for Binarized Neural Network." In 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS), pp. 66-69. IEEE, 2022.
Chen, Xizi, Jingyang Zhu, Jingbo Jiang, and Chi-Ying Tsui. "Tight compression: compressing CNN model tightly through unstructured pruning and simulated annealing based permutation." In 2020 57th ACM/IEEE Design Automation Conference (DAC), pp. 1-6. IEEE, 2020.
Chen, Xizi, Jingyang Zhu, Jingbo Jiang, and Chi-Ying Tsui. "CompRRAE: RRAM-based convolutional neural network accelerator with reduced computations through a runtime activation estimation." In Proceedings of the 24th Asia and South Pacific design automation conference, pp. 133-139. 2019.
Chen, Xizi, Jingbo Jiang, Jingyang Zhu, and Chi-Ying Tsui. "A high-throughput and energy-efficient RRAM-based convolutional neural network using data encoding and dynamic quantization." In 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 123-128. IEEE, 2018.
Zhu, Jingyang, Jingbo Jiang, Xizi Chen, and Chi-Ying Tsui. "SparseNN: An energy-efficient neural network accelerator exploiting input and output sparsity." In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 241-244. IEEE, 2018.
Zhu, Jingyang, Zhiliang Qian, and Chi-Ying Tsui. "BHNN: A memory-efficient accelerator for compressing deep neural networks with blocked hashing techniques." In 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 690-695. IEEE, 2017.
Zhu, Jingyang, Zhiliang Qian, and Chi-Ying Tsui. "Lradnn: High-throughput and energy-efficient deep neural network accelerator using low rank approximation." In 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 581-586. IEEE, 2016.
ZQian, Zhiliang, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, and Radu Marculescu. "A comprehensive and accurate latency model for network-on-chip performance analysis." In 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 323-328. IEEE, 2014.
Xue, Yuankun, Zhiliang Qian, Paul Bogdan, Fan Ye, and Chi-Ying Tsui. "Disease diagnosis-on-a-chip: Large scale networks-on-chip based multicore platform for protein folding analysis." In Proceedings of the 51st Annual Design Automation Conference, pp. 1-6. 2014.
Xue, Yuankun, Zhiliang Qian, Guopeng Wei, Paul Bogdan, Chi-Ying Tsui, and Radu Marculescu. "An efficient network-on-chip (NoC) based multicore platform for hierarchical parallel genetic algorithms." In 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), pp. 17-24. IEEE, 2014.
Qian, Zhiliang, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, and Radu Marculescu. "Svr-noc: A performance analysis tool for network-on-chips using learning-based support vector regression model." In 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 354-357. IEEE, 2013.
Qian, Zhiliang, Paul Bogdan, Chi-Ying Tsui, and Radu Marculescu. "Performance evaluation of multicore systems: From traffic analysis to latency predictions (Embedded tutorial)." In 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 82-84. IEEE, 2013.