Vignesh Suresh

I am a PhD candidate at the University of Illinois Urbana-Champaign. I am advised by Prof. Sarita Adve and I work on topics in computer architecture and systems.

My CV is here. My email is vv15@illinois.edu.

Updates:

• Feb 2026: I have successfully completed my PhD preliminary exam at UIUC! 

• Feb 2025: Sriram and I are selected as finalists for the Qualcomm Innovation Fellowship 2025.

• Oct 2024: Mozart is an SoC architecture that rethinks control and data interfaces for composing hardware accelerators through shared-memory interfaces, and was published at PACT 2024.

• Aug 2024: I interned at Qualcomm, San Diego as part of the Cloud AI group, mentored by Bob Rychlik, during the summer of 2024. My work concerned the evaluation and extension of the design for coherent shared memory in Snapdragon SoCs.

• Feb 2024: EPOCHS-1 was a multi-organization collaboration to build a scalable methodology for designing heterogeneous SoCs, and published at ISSCC 2024.

• Nov 2023: The Spandex coherence protocol has been realized in synthesizable hardware and integrated with the ESP platform here: GitHub link

• Aug 2021: I arrived at University of Illinois Urbana-Champaign for a PhD in Electrical and Computer Engineering!

• Jan 2021: I left my role at Intel. I had a great experience working with teams designing diverse system-on-chips (SoC) for use cases like ML-based video analytics and 4G/5G modems. My responsibilities includes pre-silicon RTL validation, post-silicon validation, and power and performance evaluation.

• Jun 2017: Received my B.Tech. in Electronics and Communication Engineering from Vellore Institute of Technology in 2017.