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About
He is a dedicated and motivated post-graduate student of the VLSI design field who works well in a team. He enjoys designing VLSI-based circuits and ultimately developing technologies that positively shape the world.
He urges to capture multi-domain experiences, not only professionally but also personally so that he can position himself as a strategic person rather than being a sceptical one.
Qualifications
M.Tech, VLSI Design and Nanoelectronics (2020-2022) Indian Institute of Technology Indore, CGPA: 8.92
B.Tech, Electronics and Communication Engineering (2015-2019) SKIT Jaipur, Percentage: 66.34%
Senior Secondary (2014-2015) DAV Centenary Public School Jaipur, Percentage: 79.40%
Secondary (2012-2013) DAV Centenary Public School Jaipur, CGPA: 7.8
Research Interests
Computational Memory
RRAM based Circuit Design
Analog and Digital Circuit Design
VLSI Technology
Skills
Programming languages: C, Python, SQL.
HDL: VHDL
Tools: Cadence-Virtuoso, Encounter; Mentor Graphics-ModelSim, Calibre; Synopsys-Design Vision; Xilinx-Vivado
Project
Analog In-Memory Computation Reconfigurable Architecture using RRAM (May 2021-Present)
Dr. Santosh Kumar Vishwakarma, Associate professor, Dept of EE, IIT Indore
Working on in-memory computation using RRAM cell and how its architecture can be designed in order to provide efficient results in the field of neural networks.
Design of Hybrid CMOS Non-Volatile Flip-Flop using 130nm RRAM Technology (Feb 2022-Present)
Dr.-Ing. Marc Reichenbach, Substitute Professor, Department of Technical Informatics, BTU Cottbus
Working on designing efficient CMOS-based SRAM memory using IHP130nm RRAM technology. Basic idea is to incorporate non-volatility in SRAM-based memory cells.
Designing of 5-stage Ring Oscillator (Apr 2021-May 2021)
Dr. Santosh Kumar Vishwakarma, Associate professor, Dept of EE, IIT Indore
The main purpose of this project is to design a 5-stage Ring Oscillator on the Cadence Virtuoso tool and analyze the Phase Noise, Tuning Range, and S-parameter of the designed circuit.
SRAM Memory Architecture Design (Nov 2020-Dec 2020)
Dr. Santosh Kumar Vishvakarma, Associate professor, Dept of EE, IIT Indore
Designed layout, performed physical design checks such as DRC and LVS of 6T SRAM. Done floor planning for I/O pad placement.
Arrhythmia Detection on ECG Signals by Using EMD (Sep 2020-Nov 2020)
Dr. Vivek Kanhangad, Associate professor, Dept of EE, IIT Indore
Developed an efficient arrhythmia detection algorithm based on EMD.
IoT based wearable Health Monitoring System Aug 2018-May 2019
Mr. Rahul Pandey, Assistant professor, Dept of ECE, SKIT Jaipur
In this project, we designed a wearable health monitoring system using an ATmega328 microcontroller to continuously monitor the health parameters of the body such as Heartbeat, Body temperature. The system can send the data to a remote server by using IoT.
Work Experience
Internship at Jaipur Airport: Airport Authority of India May 2018 - June 2018
Mr. Rajesh Meena: Manager-CNS
Undergone industrial training at Jaipur Airport and learned about communication systems and other
electronic equipment deployed by the authority. The training was under the Communication, Navigation &
Surveillance department of the Airport (CNS).
Internship at MEGABIZ4U Media Pvt Ltd: Startup Company July 2018 - August 2018
Ms. Varnali Sharma: C0-Founder-MEGABIZ4U Media Pvt Ltd
Worked in a team to help in Orders and Payment management for the company’s e-commerce platform.
Training also included competitive research analysis.
Publication
Varun Bhatnagar, et al., ‘Loading Effect Free MOS-only Voltage Reference Ladder for ADC in RRAMcrossbar Array’, GLSVLSI 2022 conference. (Accepted).
Patent
Noise Pollution Indicator Alarming Intensity and Frequency of Noise generated by Activities of People/Machines. Patent Application No. 201711004250
Publication Date: Feb 2017
Inventor : Mridul Bhatnagar and Varun Bhatnagar
Certifications/Training
Completed online course on VLSI System On Chip Design by Maven Silicon, (May 2021)
Participated in IEP on FPGA Based Embedded Systems â Covering Swadeshi Microprocessors organized by NIELIT Calicut, supported through C2SD (SMDP-III) Project, (Nov-Dec 2020)
Participated as Team Lead in Swadeshi Microprocessor Challenge, (Sep-Dec 2020)
Completed online Makerâs Course on Nanotechnology, (Mar-Apr 2020)
Extra-Curricular
Attended Online Faculty Development Program on Emerging Trends in VLSI and Nanoelectronics for Building Atmanirbhar Bharat Organized by Centre for Advanced Electronics (CAE) IIT Indore, (Feb 15-20, 2021)
Attended workshop on Opportunities in Research and Development in Armament Establishments (ARMREB-2020), (Aug 26, 2020)
Attended National Conference on Advancements in Nano-Electronics and Communication Technologies (ANCT-2017), (Feb 9-11, 2017)
Attended National Conference on Sustainable Engineering Applications of Material Science and Physico-Chemical Innovations (NCSEAM-2016), (Feb 26-27, 2016)
Other Information
I enjoy reading about the latest development in technology front in the world. Also, enjoy playing outdoor games whenever get the opportunity.
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