- My research interests cover architectural supports and system softwares for high performance computing. I worked on architectural supports to improve the coverage of address translation. Currently, I am improving the QoS of cache memory without any architectural modifications. I am also interested in hardware-assisted security and accelerators.
- Ph.D. Student/Research Assistant, Computer Science, KAIST, Mar. 2016 - present
- Adviser: Jaehyuk Huh
- GPA: 3.97/4.3
- Master of Science, Computer Science, KAIST, Mar. 2014 - Feb. 2016
- Adviser: Jaehyuk Huh
- GPA: 4.04/4.3
- Thesis: "Dynamic Time Slice Management Based on Cpupool in Virtualized Systems"
- Bachelor, Computer Engineering, Sungkyunkwan University, Mar. 2010 - Feb. 2014
- GPA: 4.44/4.5, Rank: 1/105
- Graduated with Honors.
- Bachelor, Business Administration, Sungkyunkwan University, Mar. 2010 - Feb. 2014
- GPA: 4.44/4.5
- Jeongseob Ahn, Chang Hyun Park, Taekyung Heo, and Jaehyuk Huh, "Accelerating Critical OS Services in Virtualized Systems with Flexible Micro-sliced Cores", in Proceedings of the 13th European Conference on Computer Systems (EuroSys), April, 2018.
- Chang Hyun Park, Taekyung Heo, Jungi Jeong, Jaehyuk Huh, “Hybrid TLB Coalescing: Improving TLB Translation Coverage under Diverse Fragmented Memory Allocations,” in Proceedings of the 44th International Symposium on Computer Architecture (ISCA), Toronto, Canada, June 2017.
- Chang Hyun Park, Taekyung Heo, Jaehyuk Huh, “Efficient Synonym Filtering and Scalable Delayed Translation for Hybrid Virtual Caching,” in Proceedings of the 43rd International Symposium on Computer Architecture (ISCA), Seoul, South Korea, June 2016.
- Improving Address Translation Capability with Virtual Caching and Delayed Segment Translation
- To solve the TLB scaling problem, proposed a novel virtual caching architecture with segment-backed delayed address translation.
- Proposed to use Bloom filter to attack the synonym problem.
- Published in ISCA 2016
- Improving Address Translation Coverage with HW-SW Hybrid TLB Coalescing
- Proposed a mechanism to encode page contiguity in page table entries to increase the TLB coverage.
- Solved the trade-offs of current TLB coverage improvement approaches in terms of HW cost, allocation flexibility, and scalability.
- Published in ISCA 2017
- Dynamic Time Slice Management based on Cpupool in Virtualized Systems
- Proposed a mechanism to solve the synchronization problem in virtualized systems due to the unawareness of physical time discontinuity by scheduling each VM in a cpupool with the preferred time slice.
- Devised a scheme to classify VMs’ time slice preferences and provide preferred time slice domains to VMs.
- My master thesis
- Improving QoS of Cache Memory using Cache Partitioning Mechanism
- Guaranteeing QoS in cache memories with an online profiling and dynamic cache partitioning mechanism.
- Other Research Projects
- Hardware-assisted Security
- Accelerators and Hardware Designs
- Programming Languages
- C, C++, Python, Verilog, VHDL
- Software Frameworks
- Xen: Implemented a system-wide profiler and per-core cache partitioning.
- MarssX86: Implemented address translation, cache partitioning, and cache prefetching.
- Pin: Implemented simple tools such as a trace generator, and memory mapping simulator.
- Gem5: Started working on Gem5 due to the limitation of MarssX86.
- EDA Tools
- Vivado, PetaLinux: Experienced the design flow from designing a custom IP to using it on a Linux system.
- Documentation Tools
- LaTeX, matplotlib
Awards & Scholarships
- KFAS Scholarship, the Korea Foundation for Advanced Studies, 2017-present
- National Scholarship, KAIST, 2014 - present
- Excellent Teaching Assistant Award, KAIST, Mar. 2018
- National Scholarship for Science and Engineering, Korea Student Aid Foundation (KOSAF), 2010-2013
- Dean's List, College of Information & Communication Engineering, Sep. 2013
- Dean's List, College of Information & Communication Engineering, Mar. 2013
- Dean's List, College of Information & Communication Engineering, Sep. 2012
- Dean's List, College of Information & Communication Engineering, Mar. 2012
- Student Representative, Department of Computer Science, KAIST, Feb 2016 - Dec 2016
- Member of Graduate Student Dormitory Council, KAIST, Mar 2016 - Feb 2017
- Student, Korea Information Technology Research Institute, Jul. 2013 - Feb. 2014
- President, Computer Security Research Club, Sungkuynkwan University, Jul 2011 - Feb 2012
- Vice President, Computer Security Research Club, Sungkyunkwan University, Mar 2011 - Jun 2011
- Teaching Assistant for Computer Organization, KAIST, Fall 2017
- Teaching Assistant for System Programming, KAIST, Spring 2017
- Teaching Assistant for Introduction to Computer Application, KAIST, Fall 2015
- Teaching Assistant for Digital System and Lab, KAIST, Spring 2015
- Teaching Assistant for System Programming, KAIST, Fall 2014
- Teaching Assistant for Introduction to Programming (Python), KAIST, Spring 2014
- Prof. Jaehyuk Huh, Department of Computer Science, KAIST, email@example.com
CV updated on 2018-05-29