Synopsys Spyglass Download

sg_shell is the spyglass tool terminal. Here I am trying to open a spyglass terminal and then run the spyglass commands. The tcl file also has some spyglass rules to perform the analysis on the opened proj. I get the following error after the jenkins pipeline is built. I have copied a part of the log file here.

2 Reading-in a Design Getting Started Analyze and improve your designs quickly and easily using Predictive Analyzer. Pre-Requisites RTL or netlist design data for the chip, IP block, or any part of the chip or IP A simulation script if possible, to define what source files are needed, in the proper order Build scripts for any VHDL libraries used Synopsys.lib files for instantiated gates and blocks HDL Compatibility Add verilog or VHDL for Verilog or VHDL design files, respectively Add 87 to command-line, if using VHDL 87 Design Input: Verilog-XL/VCS Users Provide exactly the command-line you would give to your simulator, changing the simulator name to spyglass verilog. Example: spyglass verilog srcs/*.v y../mylib +libext... +define... +incdir+ NOTE: can also read f files HDL Library Mapping HDL (Verilog and VHDL) library mapping can be achieved by spyglass lib March

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3 Design Input: MTI Users Translate your modelsim.ini file into libmap.f file as follows: The library mapping is specified using the following style, under: [LIBRARY] section L1 =./L1_path --> -lib L1./L1_path Translate your modelsim script file as follows: vmap L2 L2_path --> Put: -lib L2./L2_path into libmap.f file vcom -work LIB1 b.vhd c.vhd d.vhd --> spyglass -mixed -work LIB1 b.vhd c.vhd d.vhd -f libmap.f vlog -work LIB2 b.v c.v d.v --> spyglass -mixed -enable_precompile_vlog -work LIB2 b.v c.v d.v f libmap.f Design Input: NCSim Users Translate each of the following commands in your cds.lib/hdl.var into libmap.f file as follows: DEFINE foo --> -lib foo . Add to file libmap.f Now, translate your NCSim script commands as follows: ncvhdl -WORK ..vhdl files.. --> spyglass -mixed work vhdl files f libmap.f ncvlog -WORK ...verilog files --> spyglass -mixed -enable_precompile_vlog work ..verilog files..-f libmap.f NCSim, default is VHDL87 while for, it is VHDL93, hence: - ncvhdl ent87.vhd... --> spyglass -87 ent87.vhd..., and, - ncsim -V93 ent93.vhd.. --> spyglass ent.93.vhdl... HDL Library Compilation Compile a library using in normal manner with lib option to specify library: spyglass lib -work Add enable_precompile_vlog while compiling Verilog libraries Use dump64bit option to create libraries for 64 bit platforms Do not move compiled libraries March

4 Libraries cannot be shared between 32-bit and 64-bit platforms Design Inputs: DC/PT Shell Scripts Obtain the list of all Verilog and VHDL files, by looking at commands: - read_verilog/read_vhdl (for TCL shell scripts) - read format verilog / read format vhdl - for tool s native shell scripts ( format could also be written as f) - analyze format vhdl /analyze format verilog (DC command to analyze VHDL and Verilog files). The equivalent commands for analyzing the VHDL and Verilog design files are as follows: %> spyglass vhdl %> spyglass -verilog - the files can be specified on the command line, or, put into a file, which is then specified as f option to Resolving Library Elements Required for most advanced checks (Clocks, DFT, Constraints, LP) For instantiated cells, for each library used: - Select Appropriate library.lib (e.g., a.lib) - Run->Library Compiler (spyglass_lc mixed gateslib) - Note.sglib file created (e.g., a.sglib) - Add sglib option to Run->Options-(spyglass -sglib a.lib Handling Designware Design Ware Components Set DC_PATH variable to a Design Compiler installation: setenv DC_PATH /net/dc2003/linux Add dw switch to the command-line while running SystemVerilog Support The following SystemVerilog constructs are supported: March

6 Check your Setup Select Audit/Audit-RTL and run to check the correctness of basic design setup. Troubleshooting Syntax, elaboration, or out-of-date errors: Verilog: Re-check the file order. Include files may be out of order. Also, the files containing parameters should be placed in the file list before the files that reference those parameters. VHDL: While compiling, check file order, if not sorted, add sort on the command-line Sorting via GUI: Select the option in GUI Window->Options-Verilog or VHDL->sort Add option -hdlin_translate_off_skip_text to command line if translate_off pragma used Multiple top-levels in design view: Multiple tops are usually an indication of something wrong (For example, missing hierarchy). Multiple tops may also indicate that testbench files have been inadvertently included in the file list top option can still be used to select only the top-level you want to run (through ): -top Blackboxes: If design is showing blackboxes (Rule: DetectBlackBoxes), check, if they are intentional, or, something has been missed from the design description Hang or abnormal exit: Re-run, adding w switch and note where problem occurs (spyglass.log will be helpful). If in analysis or synthesis, note module/entity name and add command line option stop If problem in a rule, add command-line option ignorerules If design contains large inferred memories, use handlememory option March

7 Analyzing Clocks, Resets, and Domain Crossings Getting Started Find clocks and resets in an unfamiliar design Find domain crossings and check synchronization techniques used Pre-Requisites Ability to read-in the design for simpler (for example, BlockDesign/Create) analysis Compiled gate library for instantiated library cells SDC file or constraints file describing clocks and resets Reading Clocks from an SDC File Create an SGDC file containing sdcschema file (e.g., sdcschema top.sdc) Add sdc2sgdc option to run Translation converts clocks and set_case_analysis statements and will use them for CDC analysis Translated file can be viewed under spyglass_reports/sdc2sgdc Creating an SGDC Constraints File Make sure no constraints files are currently included in the analysis Select Methodology Clocks, template Find Clocks, then run, cat spyglass_reports/clock-reset/auto*.sgdc > constraints.sgdc Review file and fix clock or reset definitions if required Change domain labels to reflect which synchronous domain each clock is in March 17dc91bb1f