Silicon-on-Insulator FETs

We have developed a 2D charge-sheet model for thin film fully depleted silicon-on-insulator (SOI) multi-gate transistors that can be applied for analysis in the subthreshold as well as above threshold regime of operation. The model takes into account the short channel effects and drain induced barrier lowering and considers coupling among all gates which is very significant as the device dimensions are scaled. The model is derived based on 3D analytical potential distribution model for the device derived from Poisson's equation under gradual channel approximation and parabolic potential distribution due to short channel effect. We have applied our model on a four gate transistor named G4-FET which consists of two MOS gates and two junction-gates to offer maximum control on the conducting channel and validated our model with available data and sophisticated simulations with SILVACO tool.

Related publications:

• S. Sayed and M. Z. R. Khan, "Analytical Modeling of Surface Accumulation Behavior of Fully Depleted SOI Four Gate Transistors", Solid-State Electronics, Elsevier 81, 105-112, March 2013. (Link).

• S. Sayed, M. I. Hossain, and M. Z. R. Khan, "A Subthreshold Swing Model for Thin-Film Fully Depleted SOI Four-Gate Transistors," IEEE Transactions on Electron Devices 59, 854-857, March 2012. (Link).

• S. Sayed, M. I. Hossain, R. Huq, and M. Z. R. Khan, "Modeling of 3D potential distribution for a thin film fully depleted p-channel G4-FET," J. Electron Devices, 11, 576-582 October 2011 (Link).

• S. Sayed, M. I. Hossain, R. Huq, and M. Z. R. Khan, "Three Dimensional Modeling of SOI Four Gate Transistors," Proc. NMDC, IEEE, 383-388, October 2010. (Link).

• S. Sayed and M. Z. R. Khan, “Mathematical Modeling of Accumulation Layer Thickness of Fully Depleted G⁴-FETs,” Proc. ICECE, IEEE 795-798, December 2012. (Link).

Based on similar device structure as G4-FET, we have proposed a novel device concept that is expected to combine the advantages of BJTs and MOS transistors on SOI technology. The idea is to modulate the minority carrier density with a MOS gate on the base region of a p-n-p or n-p-n BJT structure fabricated on burried oxide. The burried oxide provides additional control on the minority carrier density which together with the front gate allows us to tune and improve the gain of the device. The fabrication steps are same as that of SOI MOSFETs and no extra fabrication steps are required. However, the device has been analyzed with simulations only.

Related publications:

• S. Sayed and M. Z. R. Khan, "Double Gate-Controlled Dual Base SOI Bipolar Junction Transistor: A Promising Candidate for High Speed Electronics", J. Electron Devices 16, 1326-1333, October 2012. (Link).