First Annual
Soft RISC-V
Systems Workshop

Talks of interest include those with the following perspectives:

• Education: professors or students presenting experiences with teaching computer architecture using RISC-V FPGA projects

• FOSS: Free and open source offerings of RISC-V processors intended for FPGAs

• Hobbyist: non-commercial / non-professional individual projects with interesting applications, or approaches to building / using RISC-V processors on FPGAs

• Research: novel features, implementations, or applications of soft RISC-V systems

• Commercial: like research, but must have a technical (not marketing) perspective

Detailed Schedule

Thursday 7 November

08:00 PST (16:00 UTC) Shreya Mehrotra, Altera, Accelerate AI Deployment with Altera's RISC-V Solution, Nios V Processors

08:30 PST (16:30 UTC) Jérôme Quévremont, Thales, CVA6, Also a Vendor-independent Open-source FPGA soft RISC-V Core

09:00 PST (17:00 UTC) Karl Wachswender, Lattice Semiconductor, Industrial Application Aligns with the Scalable Lattice RISC-V Offering

09:30 PST (17:30 UTC) Jan Gray, Gray Research LLC, All Together Now: A Common Logic Interface for Custom Instructions

10:00 PST (18:00 UTC) Break / Open Discussion

10:30 PST (18:30 UTC) Charles Papon, Individual, VexiiRiscv / Efinix: running Debian on a Softcore

11:00 PST (19:00 UTC) Marc Solé Bonet, Barcelona Supercomputing Center, SPARROW: Small and Portable AI Acceleration for RISC-V Softcores

11:20 PST (19:20 UTC) Stephan Nolting, Individual, The NEORV32 RISC-V Processor - An Introduction

11:40 PST (19:40 UTC) Yimin Gu, The University of Tokyo, Linux Capable RISC-V SoC with OpenXC7 for Educational Purposes

Friday 8 November

08:00 PST (16:00 UTC) Göran Bilski, AMD, MicroBlaze V

08:30 PST (16:30 UTC) Domingo Benitez, ULPGC Spain, Hands-on Experience for Undergraduate Computer Architecture Courses using Nios V-based Soft SoCs and Real Boards

09:00 PST (17:00 UTC) Loren Hobbs (Bluespec) and Raymond Nijssen (Achronix), Scalable RISC-V Processing with Achronix FPGAs and 2D Network on Chip

09:30 PST (17:30 UTC) Francelly Canoladino, Barcelona Supercomputing Center, Open-Source HW/SW FPGA-based Shell for RISC-V Emulation

09:45 PST (17:45 UTC) Lightning 1: Wade Fortney, Univ. of Florida, NEORV32 RISC-V for Education

09:50 PST (17:50 UTC) Lightning 2: Sallar Ahmadi-Pour, Univ. of Bremen, MicroRV32, A RISC-V Platform for Education and Research

09:55 PST (17:55 UTC) Lightning 3: Julian Kemmerer, PipelineC, A SoC in C: PipelineC HDL and RISC-V

10:00 PST (18:00 UTC) Break / Lightning Round Posters

10:30 PST (18:30 UTC) Ken O'Hagan, Microchip, Mi-V RV32 Soft RISC-V Processor

11:00 PST (19:00 UTC) Bruno Levy, INRIA, Learn-FPGA and FemtoRV: from blinky to RiscV

11:30 PST (19:30 UTC) Rishiyur Nikhil, Bluespec, Catamaran: for Quick FPGA Bringup of Linux-capable RISC-V CPUs