Venkata Sreekanth Balijabudda

balijavenkatasreekanth@gmail.com, github.com/fairpulse/ 

Education:

1. Indian Institute of Technology (IIT), Kharagpur, 2017-present: CGPA 8.71

Ph.D. (submitting) under the supervision of:

Prof. Rajat Subhra Chakraborty, CSE and Prof. Indrajit Chakrabarti, EECE

2. Master of Technology in Digital Systems and Computer Electronics

Jawaharlal Nehru Technological University, Hyderabad, 2013-16 with 80.12 %

3. Bachelor of Technology in Electronics and Communications Engineering

Jawaharlal Nehru Technological University, Hyderabad, 2009-13 with 86.96 %

Research Experience:

2017-19: Senior Research Fellow, “Hardware security in the context of a connected world: threats and mitigations”, delivered to Bhabha Atomic Research Centre, Mumbai.

Teaching Experience:

1. April 2024, Workshop on “Basic understanding of FPGA and Verilog for control applications”, IEEE Kharagpur section, Department of Electrical Engineering, IIT Kharagpur

2. March 2024, Workshop on "Migration from Classical to Quantum-safe Cryptography: A Workshop on Future-Ready Security", BITS BioCyTiH Foundation, BITS Goa

3. January 2024, Training Course on “Cryptanalysis”, ACTS-CDAC, Bharat Electronics Limited, Bengaluru

4. 2016-17 Assistant Professor at Department of ECE, Sreenidhi Institute of Science and Technology, Hyderabad

Teaching Assistantship:

Computer Organization and Architecture, Switching Circuits and Logic Design, Programming and Data Structures, Microprocessor Design

Ph.D. Research:

Hardware Security, Cryptography, Machine Learning, and Digital VLSI design

Programming Skills: C, C++, Python, MIPS, TCL

Hardware Description Skills: Verilog, HSPICE, Cadence Virtuoso, Synopsys IC Compiler

Awards and Honors: Awarded gold medal for competence in UG.

Patents:

1. "Trust Establishment of Program Binary on Field Programmable Gate Array using Physically Unclonable Functions”, Patent Application No. 202431037356, Intellectual Property India, May 2024.

2. “Untrusted Hardware Module Identification and Reporting for Secure System Implementation on Field Programmable Gate Array Platform”, Patent Application No. 202431003427, Intellectual Property India, January 2024.

Publications:

1. B.V. Sreekanth, I. Chakrabarti and, R. S. Chakraborty, “Design, Implementation and Characterization of a Novel Robust-by-Construction Arbiter PUF Circuit on Xilinx FPGAs”, 33rd Asian Test Symposium (ATS), 2024.

2. B.V. Sreekanth, K. Acharya, R. S. Chakraborty, and I. Chakrabarti, “Theoretical Enumeration of Deployable Single-output Strong PUF Instances based on Uniformity and Uniqueness Constraints”, ICISS 2023, Springer Lecture Notes in Computer Science, Volume 14424.

3. B.V. Sreekanth, D. Thapar, P. Santikellur, R. S. Chakraborty, and I. Chakrabarti, “Design of a Chaotic Oscillator based Model Building Attack Resistant Arbiter PUF”, 2019 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 2019, pp. 1-6.

4. B.V. Sreekanth, Rohin Koduri, and Dr. G.V. Maha Lakshmi, “Single View based Motion Analysis in High Speed Imaging Applications: A theoretical Framework,” International Journal for Scientific Research & Development (IJSRD), Vol.4, Issue 10, 2016, pp 387-392.

5. Swaroopa, B.V. Sreekanth, I. Chakrabarti, and R.S. Chakraborty, “PUFBind: Physical Unclonable Function Enabled Lightweight Simultaneous Platform and Program Binary Authentication System for Field Programmable Gate Arrays”, ACM Transactions on Computer Systems, Under review.

University and Social services:

Active Reviewer for IEEE “TCAD”, “INDICON”, and “ISCAS” 2024

Volunteer at Child Rights and You (CRY), IIT Kharagpur Chapter