Systems for Post-Moore Architectures

The 11th Workshop on Systems for Post-Moore Architectures

co-located with Eurosys 2021

Cancelled this year.

Dear friends of SPMA,

After much deliberation we decided that it would be better to skip SPMA workshop this year. SPMA has always followed an open, proceeding-free format, with the primary goal of providing an opportunity to discuss new ideas with same-minded people rather than a regular venue for publishing papers. Sadly, we feel that the COVID-imposed virtual format is likely to impede the fulfillment of these goals. For this reason, we decided that SPMA will "go on hiatus" this year.

We do hope very much that we will be able to run the workshop physically next year and we encourage you to submit your papers and participate in the future!

Best regards

Mark & Zsolt

Topics

Modern systems feature a wide variety of new processing accelerator-rich architectures, with computations performed in-memory, in-network, in Smart I/O devices, and numerous accelerators. To achieve high performance, efficiency and cost-effectiveness on these platforms, application developers will need exploit low-level hardware features to a much greater extent than before, challenging the traditional software paradigms. At the same time, these traits are transcending single host systems as emerging integrated fabric technologies enable disaggregated rack-scale system designs in data centers, with hundreds of GB/s, sub-microsecond interconnects blurring traditional machine boundaries.

The workshop (the successor of SFMA workshop series) brings together researchers in operating systems, language runtime, virtual machine and architecture communities to present and discuss their system building experiences with the emerging hardware architectures.

Topics of interest include (but are not limited to):

  • Operating System and programming environments for future hardware,

  • Systems and applications on programmable switches

  • Hybrid scale-up/scale-out system designs

  • Energy efficiency, fault tolerance and resource management on future multi-core architectures,

  • Architectural support for systems-level software, and

  • Case studies of system-level software design for current or future multi-core hardware.

Publication policy

The papers will be distributed to workshop participants via the website, but will not be published via ACM Digital Library with the aim to encourage the submission of early-stage work soliciting feedback from the community. This policy allows later submission to more formal venues, e.g., EuroSys, OSDI, or ISCA.

Workshop format

We plan to have 4-8 presentations of accepted papers, and 3 keynote speakers with world-established expertise in the field of interest for the workshop. The workshop will conclude with a panel discussion.

Paper submission

Authors are invited to submit original work that exposes a new problem, advocates a specific solution, or reports on actual experience. In addition, this year we are also considering already published papers for those who wishes to expose their work to a new audience. The submissions are of three types: short papers (5 pages) or position papers (1-2 pages - can be extended after acceptance) , and extended abstract (1 page) for already published papers. The page count does not include references. Papers should be submitted using the standard two-column ACM SIG proceedings or SIG alternate template.

Paper submission is single-blind.

Submission site: TBA


For any information, please contact workshop organizers