2.5D/3D chiplet modeling and verification
HBM core / interconnect / PDN modeling and verifcation
ReRAM, MRAM, SRAM, eDRAM, and new memory device modeling
System-level PIM / Neuromorphic modeling and validation
Mixed-Signal In-Memory Computing Macro for Edge Devices
Embedded Memories for PIM in CMOS Logics
PIM System Modeling with XMODEL
Verilog-Based Automatic Generation of Analog Circuits
Synthesizable On-Chip Waveform Monitoring System for Low-Voltage SoCs