Hello! I am currently an SoC (Systems-on-Chip) architect at Qualcomm, working on modeling and designing augmented/virtual reality (AR/VR) chip architectures and systems that continues to empower our daily lives in various ways. Earlier, I graduated with my PhD in Computer Engineering from School of Computing and Augmented Intelligence (SCAI), Arizona State University with Outstanding Ph.D. Graduate Award, with my dissertation titled, "Agile and Explainable Methodology for Designing Efficient Domain-Specific Architectures". 

Topical Expertise: My R&D works and infrastructures over the last decade have enabled the efficient processing of various critical applications on domain-specific processors and systems-on-chip in an agile and sustainable manner. This includes compilation and mapping optimizations, early-phase design execution cost modeling, cycle-level simulations, and bottleneck characterization of various domain-specific architectures, language and frameworks for more automated architectural designs, efficient dense and sparse tensor computations of ML and various embedded applications, and explorations of efficient hardware/software co-designs through systematic heuristics and machine learning. 

R&D Visibility and Impact: My research has been published and regularly referred by leading researchers in academia and industry in the flagship ACM/IEEE conferences and journals in relevant fields (design automation, embedded systems, and computer architecture, such as ASPLOS, DAC, Proceedings of the IEEE and CODES+ISSS) and industry patents. My works have also been featured in premier industrial and global forums. Some of my early works and infrastructures laid foundation for various industry and academic groups to build their early-stage design exploration infrastructures for various multimedia, wearables, and AI accelerators. In addition, my R&D works and vision previously contributed to ASU's project acceptance and participation in highly competitive national projects (including Semiconductor Research Corporation's AI Hardware program, NSF/Intel Research Center on Computer Assisted Heterogeneous Programming) and a new topical course at ASU (on Machine Learning Accelerator Design; See Reading List). It also impacted findings to the report for the first NSF (National Science Foundation) workshop on Designing Sustainable Computing Systems. My works had been featured by various organizations, media, magazines, and social media, including ACM Tech news, Communications of the ACM blog, front-page ASU news, insideHPC, IEEE Bridge and IEEE Eta Kappa Nu (HKN), DeepAI, Hacker news, and Intel Labs Select Publications. 

Industry Experience, Honors, and Professional Activities: My prior industry experiences range from developing compiler optimizations for wide-scale commodity embedded systems to digital design and verification for FPGA-based processors and ASICs. I also piloted several projects in competitive programs with academics and industry researchers, including for heterogeneous and AI computing systems. I am a recipient of several honors, awards, and fellowships, including Silver Medal from ACM for Student Research Competition, Outstanding PhD Award from ASU, Outstanding Research and Teaching Assistant Awards, and Doctoral Dissertation Fellowship from Graduate College at ASU. I regularly serve in various mentorship and outreach programs, vision workshops for future computing systems research, and as an associate editor, organization/program committee member, or reviewer for the leading ACM/IEEE conferences, journals, and workshops.