- Computer Architecture
- Memory and Storage Systems
- Near-data Processing
- Domain-specific Accelerators
- Architectural Support for Security
- 2017 - 2018 Research Scientist (Postdoctoral Researcher) at IBM T.J. Watson Research Center
- 2015 - 2017 Senior Engineer at Samsung Electronics
- 2008 - 2015 Research Assistant at KAIST
- 2009 Research Intern at ETRI
- 2006 - 2008 Software Engineer Intern at SSM (Samsung Software Membership)
AWARDS AND HONORS
- 2014 Best Paper Nominee, IEEE International Conference on Computer Design (ICCD'14)
- 2013 Best Paper Award, Design Automation and Test in Europe Conference (DATE’13)
- 2010 Best Paper Award, IEEE International Conference on Computer Design (ICCD’10).
- 2018 IEEE International Conference on Computer Design (ICCD)
- 2018 The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC)
- 2018 The International Symposium on Low Power Electronics and Design (ISLPED)
- 2017 ACM Transaction on Architecture and Code Optimization
- 2017 IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems
- 2017 IEEE Computer Architecture Letters
- Seokin Hong, Prashant J. Nair, Bulent Abali, Alper Buyuktosunoglu, Kyu-Hyoun Kim, and Michael Healy, "Attache: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads", accepted for MICRO 2018.
- Michael Healy and Seokin Hong, "CramSim: Controller and Memory Simulator", 2017 International Symposium on Memory Systems. ACM, Washington DC, USA, 2017.
- Yebin Lee, Hyeonggyu Kim, Seokin Hong and Soontae Kim, "Partial Row Activation for Low-Power DRAM System", 2017 IEEE International Symposium on High Performance Computer Architecture, Austin, TX, 2017.
- Seokin Hong, Soontea Kim, "Designing A Resilient L1 Cache Architecture to Process Variation-induced Access-time Failures", IEEE Transactions on Computers, Volume 65, Number 10, Oct. 2016, pp. 2999-3012.
- Seokin Hong, Soontea Kim, "A Low-cost Mechanism Exploiting Narrow-width Values for Tolerating Hard Faults in ALU", IEEE Transactions on Computers, Volume 64, Number 9, Sep. 2015, pp. 2433-2446.
- Tayyeb Mahmood, Seokin Hong, Soontae Kim, "Ensuring cache reliability and energy scaling at near-threshold voltage with Macho", IEEE Transactions on Computers, Volume 64, Number 6, Jun. 2015, pp. 1694-1706.
- Seokin Hong, Jongmin Lee, Soontae Kim, "Ternary Cache: Three-valued MLC STT-RAM Caches", IEEE International Conference on Computer Design, Seoul, Korea, Oct. 19-22, 2014.
- Seokin Hong, Soontae Kim, "AVICA: An Access-time Variation Insensitive L1 Cache Architecture", Design Automation and Test in Europe Conference, Grenoble, France, March 18-22, 2013.
- Yebin Lee, Soontae Kim, Seokin Hong, Jongmin Lee, "Skinflint DRAM System: Minimizing DRAM Chip Writes for Low Power", IEEE International Symposium on High Performance Computer Architecture, Shenzhen, China, Feb., 2013.
- Tayyeb Mahmood, Soontae Kim, Seokin Hong, "Macho: A Failure Model-oriented Adaptive Cache Architecture to enable Near-Threshold Voltage Scaling", IEEE International Symposium on High Performance Computer Architecture, Shenzhen, China, 2013.
- Soontae Kim, Jesung kim, Jongmin Lee, Seokin Hong, "Residue Cache: A Low-Energy Low-Area L2 Cache Architecture via Compression and Partial Hits", IEEE/ACM International Symposium on Microarchitecture, Brazil, Dec. 3-7, 2011.
- Jongmin Lee, Seokin Hong, and Soontae Kim, "TLB Index-based Tagging for Cache Energy Reduction", ACM/IEEE International Symposium on Low Power Electronics and Design,Fukuoka, Japan, Aug. 1-3, 2011.
- Seokin Hong and Soontae Kim, "Lizard: energy-efficient hard fault detection, diagnosis and isolation in the ALU", IEEE International Conference on Computer Design, Amsterdam, Netherlands, Oct. 3-6, 2010.
- Seokin Hong, Soontae Kim, "TEPS: Transient error protection utilizing sub-word parallelism", IEEE computer Society Annual International Symposium on VLSI, Tampa, FL, USA, May 13-15, 2009.