I am an Assistant Professor in the School of Computer Science and Engineering at Kyungpook National University (KNU). My major research experiences and interests include the design of low power, reliable, and high-performance microarchitectures and memory systems. I received the PhD in Computer Science from KAIST, Korea, in 2015. Prior to joining KNU, I was a Research Scientist (Postdoctoral Researcher) at IBM TJ Watson Research Center and a Senior Engineer at Samsung Electronics.

CONTACT

NOTICE!!

I'm actively recruiting highly motivated students who want to do research in computer architecture and systems. Preferred majors include computer science, computer engineering, and electrical engineering. If you are interested in joining my lab, please contact me at seokin@knu.ac.kr.

RESEARCH INTERESTS

  • Processor Architectures
    • CPU/GPU architectures
    • Architectural Support for Security
  • Memory and Storage Systems
    • DRAM Systems
    • Storage Class Memory (SCM)
    • Heterogeneous Memory Systems
    • Secure Memory
  • Near-Data Processing
  • Memory-centric Computing Systems
  • AI Acceleration

LAB MEMBERS

  • Seungmin Shin
  • Chanhui Seok
  • Beomjun Kim

PUBLICATIONS

  • [Top-tier] Seokin Hong, Bulent Abali, Alper Buyuktosunoglu, Michael Healy, and Prashant J. Nair, "Touche: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads", To appear in IEEE/ACM International Symposium on Microarchitecture (MICRO'19), 2019.
  • [SCIE] Wonyoung Lee, Mincheol Kang, Seokin Hong, Soontae Kim, "Inter-Page-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages", To appear in IEEE Transactions on Very Large Scale Integration Systems (TVLSI)
  • [Top-tier] Tian Jin and Seokin Hong, "Split-CNN: Splitting Window-based Operations in Convolutional Neural Networks for Memory System Optimization", International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '19), New York, NY, USA, 2019.
  • [Top-tier] Seokin Hong, Prashant J. Nair, Bulent Abali, Alper Buyuktosunoglu, Kyu-Hyoun Kim, and Michael Healy, "Attache: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads", IEEE/ACM International Symposium on Microarchitecture (MICRO), Fukuoka, Japan, Oct., 2018.
  • [Etc] Michael Healy and Seokin Hong, "CramSim: Controller and Memory Simulator", International Symposium on Memory Systems(MEMSYS), Washington DC, USA, 2017.
  • [Top-tier] Yebin Lee, Hyeonggyu Kim, Seokin Hong and Soontae Kim, "Partial Row Activation for Low-Power DRAM System", IEEE International Symposium on High Performance Computer Architecture (HPCA), Austin, TX, 2017.
  • [SCI] Seokin Hong, Soontea Kim, "Designing A Resilient L1 Cache Architecture to Process Variation-induced Access-time Failures", IEEE Transactions on Computers, Volume 65, Number 10, Oct. 2016, pp. 2999-3012.
  • [SCI] Seokin Hong, Soontea Kim, "A Low-cost Mechanism Exploiting Narrow-width Values for Tolerating Hard Faults in ALU", IEEE Transactions on Computers, Volume 64, Number 9, Sep. 2015, pp. 2433-2446.
  • [SCI] Tayyeb Mahmood, Seokin Hong, Soontae Kim, "Ensuring cache reliability and energy scaling at near-threshold voltage with Macho", IEEE Transactions on Computers, Volume 64, Number 6, Jun. 2015, pp. 1694-1706.
  • [Major] Seokin Hong, Jongmin Lee, Soontae Kim, "Ternary Cache: Three-valued MLC STT-RAM Caches", IEEE International Conference on Computer Design (ICCD), Seoul, Korea, Oct. 19-22, 2014.
  • [Major] Seokin Hong, Soontae Kim, "AVICA: An Access-time Variation Insensitive L1 Cache Architecture", Design Automation and Test in Europe Conference (DATE), Grenoble, France, March 18-22, 2013.
  • [Top-tier] Yebin Lee, Soontae Kim, Seokin Hong, Jongmin Lee, "Skinflint DRAM System: Minimizing DRAM Chip Writes for Low Power", IEEE International Symposium on High Performance Computer Architecture (HPCA), Shenzhen, China, Feb., 2013.
  • [Top-tier] Tayyeb Mahmood, Soontae Kim, Seokin Hong, "Macho: A Failure Model-oriented Adaptive Cache Architecture to enable Near-Threshold Voltage Scaling", IEEE International Symposium on High Performance Computer Architecture(HPCA), Shenzhen, China, 2013.
  • [Top-tier] Soontae Kim, Jesung kim, Jongmin Lee, Seokin Hong, "Residue Cache: A Low-Energy Low-Area L2 Cache Architecture via Compression and Partial Hits", IEEE/ACM International Symposium on Microarchitecture (MICRO), Brazil, Dec. 3-7, 2011.
  • [Major] Jongmin Lee, Seokin Hong, and Soontae Kim, "TLB Index-based Tagging for Cache Energy Reduction", ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED),Fukuoka, Japan, Aug. 1-3, 2011.
  • [Major] Seokin Hong and Soontae Kim, "Lizard: energy-efficient hard fault detection, diagnosis and isolation in the ALU", IEEE International Conference on Computer Design (ICCD), Amsterdam, Netherlands, Oct. 3-6, 2010.
  • [Etc] Seokin Hong, Soontae Kim, "TEPS: Transient error protection utilizing sub-word parallelism", IEEE computer Society Annual International Symposium on VLSI (ISVLSI), Tampa, FL, USA, May 13-15, 2009.


PROFESSIONAL EXPERIENCES

  • 2017 - 2018 Research Scientist (Postdoctoral Researcher) at IBM T.J. Watson Research Center
  • 2015 - 2017 Senior Engineer at Samsung Electronics
  • 2008 - 2015 Research Assistant at KAIST
  • 2009 Research Intern at ETRI
  • 2006 - 2008 Software Engineer Intern at SSM (Samsung Software Membership)

AWARDS AND HONORS

  • 2014 Best Paper Nominee, IEEE International Conference on Computer Design (ICCD'14)
  • 2013 Best Paper Award, Design Automation and Test in Europe Conference (DATE’13)
  • 2010 Best Paper Award, IEEE International Conference on Computer Design (ICCD’10).

PROFESSIONAL ACTIVITIES

  • Program Committee
    • IEEE International Conference on Computer Design (ICCD), 2019
  • Reviewer
    • IEEE International Conference on Computer Design (ICCD)
    • The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC)
    • The International Symposium on Low Power Electronics and Design (ISLPED)
    • ACM Transaction on Architecture and Code Optimization
    • IEEE Transaction on Computer
    • IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems
    • IEEE Computer Architecture Letters
    • ETRI journal

TEACHING

  • Computer Architecture (Fall 2018, English)
  • System Programming (Fall 2018, English)