News
03/2025: Dr. Sachin Taneja was featured as a researcher in Intel Labs' "Featured Researchers" series. [link]
02/2025: Our work on first ASIC implementation of masked SHA2-HMAC hardware accelerator has been accepted for oral presentation at IEEE Custom Integrated Circuits Conference, 2025 in Boston [link]
06/2024: We recently presented our work on Fault-injection attack resistant AES using isomorphic composite Galois fields (GF) at IEEE VLSI Symposium, 2024 in Hawaii [IEEE paper link].
03/2024: Dr. Taneja is invited to serve in Technical Program Committee for IEEE Asian Solid-State Circuits Conference (A-SSCC), 2024.
12/2023: Our US patent application to cover the novel class of architecture featuring "Unified TRNG and Cryptographic Core" is published online [US patent link].
10/2023: Dr. Taneja is invited to continue serving as an Associate Editor for the IEEE Transactions on Circuits and Systems-II (TCAS II) for the next term (2024 to 2025).
06/2023: We recently presented our Privacy-Preserving Mutual Authentication Accelerator using PUF and AES with SCA and ML resilience at IEEE VLSI Symposium, 2023 in Kyoto [IEEE paper link].
02/2021: I am honored to receive the IEEE Solid-State Circuits Society Predoctoral Achievement Award for 2020-2021 at 2021 ISSCC [SSCS Website link, ISSCC SRP Award Ceremony Link].
Research Interests
Summary of my Ph.D. research work boils down to exploration of efficient and novel circuits architectures to convert the entropy in integrated circuits (IC) into random digital bits widely used to secure microchips down to hardware level.
My current research focus is in design of hardware security circuit primitives and systems. I am also actively looking in physical security and in-memory compute accelerator domain.
For discussion related to my research work and collaborations, feel free to reach me at sachin.taneja@u.nus.edu.
Professional Activities and Service
Technical Program Committee Member, IEEE Asian Solid-State Circuits Conference (A-SSCC) [Link], 2022 - present
Associate Editor, IEEE Transactions on Circuits and Systems II (TCAS-II) [Link], 2022 - present
Awards
2020-2021 IEEE SSCS Predoctoral Achievement Award [Link]
2020 IEEE CASS Student Travel Grant Award
2019 ISSCC Student Travel Grant Award, 2019 IEEE VLSI Symposium Student Travel Grant Award
Industry Experience
Research Scientist, Intel Circuit Research Labs, 2021-Present.
R&D Engineer, Synopsys India Pvt. Ltd., 2014-2016
R&D Intern, Synopsys India Pvt. Ltd., 2013-2014
Education
Ph.D., Department of Electrical and Computer Engineering, National University of Singapore, 2017- 2021
B.Tech., Bharati Vidyapeeth's College of Engineering, GGSIPU, 2009-2013
Academic Experience
Research Engineer, Department of Electrical and Computer Engineering, National University of Singapore, 2016-2017
Research Projects
Privacy-Preserving Mutual Authentication Accelerator
Mutual authentication with privacy using strong PUF coupled with Crypto for SCA and ML resilience [VLSI 2023]
Physically Unclonable Functions (PUF)
Fully Synthesizable weak PUF for low design effort and high stability [JSSC 2018] [A-SSCC 2017]
PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Secure-Key Generation via Sensor Fusion [JSSC 2021] [ESSCIRC 2019]
True Random Number Generators (TRNG)
Fully Synthesizable Unified True Random Number Generator and Cryptographic Core [JSSC 2021] [SSC-L 2020]
Unified True Random Number Generators (TRNG) and Physically Unclonable Functions (PUF)
Unified In-memory TRNG and Multi-Bit PUF [JSSC 2022] [ISSCC 2021]
Private-Key Cryptographic Accelerator
Key-scaling and ultra-low energy SIMON cryptographic accelerator [ISCAS 2020] [arXiv 2018]
Energy-Efficient Security Systems
Security scalable protocols for secure systems [IOTJ 2019]
Research Reviews
Publications
Journal:
S. Taneja, V. K. Rajanna and M. Alioto, "In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security," in IEEE Journal of Solid-State Circuits, vol. 57, no. 1, pp. 153-166, Jan. 2022 (invited).
S. Taneja and M. Alioto, "Fully Synthesizable Unified True Random Number Generator and Cryptographic Core," in IEEE Journal of Solid-State Circuits, vol. 56, no. 10, pp. 3049-3061, Oct. 2021 (invited).
S. Taneja and M. Alioto, "PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion," in IEEE Journal of Solid-State Circuits, vol. 56, no. 7, pp. 2182-2192, July 2021.
S. Taneja and M. Alioto, “Fully-Synthesizable All-Digital Unified Dynamic Entropy Generation, Extraction and Utilization within the Same Cryptographic Core” accepted for publication in IEEE Solid-State Circuits Letters (invited).
M. Naveed Aman, S. Taneja, B. Sikdar, K. C. Chua and M. Alioto, "Token-Based Security for the Internet of Things with Dynamic Energy-Quality Tradeoff," in IEEE Internet of Things Journal, vol. 6, no. 2, pp. 2843-2859, April 2019.
S. Taneja, A. B. Alvarez and M. Alioto, "Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm," in IEEE Journal of Solid-State Circuits, vol. 53, no. 10, pp. 2828-2839, Oct. 2018 (invited).
Conference:
S. Taneja, V. Suresh, R. Kumar, V. De and S. Mathew, "218Kauth/s, 3nJ/auth SCA/ML-Resistant Privacy-Preserving Mutual Authentication Accelerator with a Crypto-Double-Coupled PUF in 4nm class CMOS," 2023 IEEE Symposium on VLSI Technology and Circuits, Kyoto, Japan, 2023, pp. 1-2.
V. K. Rajanna, S. Taneja and M. Alioto, "SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1,459 TOPS/W in 28nm," ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, pp. 127-130.
S. Taneja, V. K. Rajanna and M. Alioto, "36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security," 2021 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2021, pp. 498-500.
S. Taneja and M. Alioto, “Deep Sub-pJ/Bit Low-Area Energy-Security Scalable SIMON Crypto-Core in 40 nm,” accepted in 2020 IEEE International Symposium on Circuits and Systems (ISCAS).
S. Taneja and M. Alioto, “PUF-based Key Generation with Design Margin Reduction via In-Situ and PVT Sensor Fusion,” 2019 IEEE European Solid-State Circuits Conference (ESSCIRC).
M. Alioto and S. Taneja, "Enabling Ubiquitous Hardware Security via Energy-Efficient Primitives and Systems: (invited)," 2019 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2019, pp. 1-8.
S. Taneja, A. Alvarez, G. Sadagopan and M. Alioto, "A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8–1.0V in 40nm," 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), Seoul, 2017, pp. 301-304.
Patents
S. Taneja, V. K. Rajanna and M. Alioto, “Method and Apparatus for Unified Dynamic and Multibit Static Entropy Generation inside Embedded Memory”, Singapore patent application, 10202100753U, January 2021.
S. Taneja and M. Alioto, “Method and Apparatus for True Random Number Generation within Cryptographic Hardware”, Singapore patent application, 10202008065R, August 2020.
S. Taneja, V. Verma, P. Singh and S. K. Jain “Sensing scheme for high speed memory circuits with single ended sensing”, US Patent US20160336076A1, November 2016, granted.
Research Projects Testchips
