Minwoo Kim
Building E10, Room #204, Chungbuk National University
E-Mail : kmw11228@chungbuk.ac.kr
Education
SEP. 2024 - Present
M.S. School of Electronic Engineering,Chungbuk National University, Cheongju, Republic of Korea.
MAR. 2018 - Feb. 2022
B.S. School of Electronic Engineering,Chungbuk National University, Cheongju, Republic of Korea.
Research Interest
- Fabrication of Semiconductor Devices
Recent: Control of process parameters including temperature,
time, and functional settings for process optimization
- Reliablity of Semiconductor Devices
Recent: Recovery device Insulator layer Interface trap,
Extract trap density from Capacitance - Voltage Measure
- Simulation of Semiconductor Devices
Parastic bottom leakage of Nanosheet FET , Trench gate of SiC Power MOSFET
Skills
- Device Fabrication Processing
(Deuterium Annealing(LTDA, RDA), Wet Etch and Cleanning, Photo lithography, Spin coater, Mask aligner
- Device Characterization
(Probe Station (Keithley 4200A, B1500), LCR Meter(HP 4284-SCS))
(Optical Microscope(LV 150NA))
(Cryogenic probe station & Hot chuck probe station)
- TCAD Simulation of Semiconductor Devices
(Synopsys Sentaurus)
- Others
(Excel(VBA), Origin 2024, COMSOLs,Python, Jetson Nano Design [YOLO-5 Model] )
Publications(SCIE)
- M.-W. Kim, H.-J. Park, M.-K. Lee, E.-C. Yun, S.-M. Kang, D.-E. Bang, T.-H. Kil, D. Sohn, and J.-Y. Park*, "Study on the Impact of Deuterium Annealing Duration on MOSFET Performance", Semicond. Sci. Technol., vol. xx, no. x, pp. xxxx-xxxx, in press.
- D. Sohn, M.-K. Lee, D.-E. Bang, H.-J. Park, E.-C. Yun, S.-M. Kang, M.-W. Kim, H. Jeon*, and J.-Y. Park*, "Wrap-Around Word-Line DRAM Cell Transistor Enabling Enhanced Read/Write Speed", IEEE Trans. Electron Devices, vol. xx, no. x, pp. xxxx-xxxx, in press.
- E.-C. Yun, H.-J. Park, M.-K. Lee, T.-H. Kil, J.-W. Yeon, M.-W. Kim, D. Sohn, and J.-Y. Park*, "Demonstration of Rapid Deuterium Annealing for High-Performance MOSFETs with Reduced Thermal Budget", IEEE Trans. Electron Devices, vol. xx, no. x, pp. xxxx-xxxx, in press.
- D.-E. Bang, M.-K. Lee, E.-C. Yun, T.-H. Kil, H.-J. Park, J.-W. Yeon, M.-W. Kim, S.-J. Jeon, A-Y. Kim, and J.-Y. Park*, "Junction Depth Optimization in Trench Gate Nanosheet FETs for Reduced Off-State Current", Silicon, vol. xx, no. x, pp. xxxx-xxxx, in press.
- S.-J. Jeon, H.-J. Park, S.-J. Chang, M.-K. Lee, E.-C. Yun, T.-H. Kil, J.-W. Yeon, M.-W. Kim, and J.-Y. Park*, "First Demonstration of Rapid Deuterium Annealing for Interface Trap Reduction in HKMG MOSFETs", Semicond. Sci. Technol. vol. 40, no. 8, pp. 1-5, Aug. 2025.
- M.-K. Lee, H.-J. Park, T.-H. Kil, J.-W. Yeon, E.-C. Yun, M.-W. Kim, and J.-Y. Park*, "W-Shaped Silicon Channels to Increase the Channel Perimeter and Improve the Output Current of Multi-Bridge-Channel FETs", Silicon, vol.17, pp. 817–823, Feb. 2025.
- T.-H. Kil, J.-W. Yeon, H.-J. Park, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-M. Kang, and J.-Y. Park*, "Low-Temperature Deuterium Annealing for HfO2 /SiO2 Gate Dielectric in Silicon MOSFETs", IEEE J. Electron Devices Soc., vol. 12, no. 1, pp. 1030-1033, Dec. 2024.
Publications(Domestic)
- S.-M. Kang, Y.-J. Choi, H.-J. Park, T.-H. Kil, J.-W. Yeon, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, M.-S. Kim*, and J.-Y. Park*, "Study on Multiple Post-Metallization Annealing for Enhancing the Performance and Reliability of Silicon MOSFETs", Trans. Electr. Electron. Mater., vol. 38, no. 2, pp. 187–192, Mar. 2025. [ Website ]
- A-Y. Kim, D.-E. Bang, H.-J. Park, T.-H. Kil, J.-W. Yeon, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, M.-S. Kim, and J.-Y. Park*, "Study on Hetero Gate Dielectrics to Reduce Ambipolar Current in Nanosheet Tunneling FETs", Trans. Electr. Electron. Mater., in press.
Patents
-박준영, 이문권, 연주원, 박효준, 길태현, 윤의철, 김민우, 전수진,
"임베디드 게이트 구조를 갖는 나노시트 반도체 소자", KR 10-2024-0196503, 2024.12.26
-박준영, 윤의철, 김민우, 강상민,
"반응기 챔버 및 이를 포함하는 급속 저온 중수소 열처리 시스템", KR 10-2025-0064149, 2025.05.16.
-박준영, 손돌, 김민우, 연주원, 박효준, 이문권, 윤의철,
"브이-노치 메탈 접촉 구조를 갖는 나노시트 반도체소자 및 그의 제조방법", KR 10-2025-0080331, 2025.06.18.
Conferences
J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, A-Y. Kim, S.-M. Kang, D.-E. Bang, and J.-Y. Park*, "Low Temperature Deuterium Annealing for Improved Immunity against Hot-Carrier Injection in HKMG MOSFETs", The 32nd Korean Conference on Semiconductors, Feb. 2025.
M.-K. Lee, H.-J. Park, E.-C. Yun, J.-W. Yeon, T.-H. Kil, M.-W. Kim, S.-J. Jeon, D.-E. Bang, D. Sohn, A-Y. Kim, S.-M. Kang, and J.-Y. Park*, "Partial Trench Gate Nanosheet FETs for Enhanced ION/ IOFF Ratio", The 32nd Korean Conference on Semiconductors, Feb. 2025.
D.-E. Bang, J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, A-Y. Kim, S.-M. Kang, and J.-Y. Park*, "Junction Depth Engineered Trench Gate Nanosheet FETs for Suppressing Leakage Current in Parasitic Substrate Channels", The 32nd Korean Conference on Semiconductors, Feb. 2025.
A-Y. Kim, J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, D.-E. Bang, S.-M. Kang, and J.-Y. Park*, "Hetero-Gate Dielectric Structures for Reducing Ambipolar Current in Nanosheet Tunneling FETs", The 32nd Korean Conference on Semiconductors, Feb. 2025.
T.-H. Kil, J.-W. Yeon, H.-J. Park, D.-E. Bang, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, A-Y. Kim, S.-M. Kang, and J.-Y. Park*, "Material Engineering of Inner Spacer in Nanosheet FETs to Reduce Off-State Current", The 32nd Korean Conference on Semiconductors, Feb. 2025.
Research Projects
Teaching Assistant
- Teaching Assistant for '반도체소자공정실험', Fall, 2024