Design Space Exploration

Design problems are ubiquitous in scientific and industrial achievements. Scientists design experiments to gain insights into natural phenomena, and engineers design machines to execute tasks more efficiently. These choices are often complex, high-dimensional, and interdependent, which makes it hard for developers to reason about. For instance, optimizing parallel applications in hardware accelerators require several design choices that trade off memory latency, runtime, energy, and resource usage.

We introduce a new methodology and corresponding software framework, HyperMapper, which handles multi-objective optimization, unknown feasibility constraints, discrete variables, and injection of user prior knowledge. These features are common requirements in the optimization of design choices for parallel architectures and HyperMapper is the only framework that simultaneously supports them all. In this tutorial we will introduce HyperMapper and give comprehensive hands-on examples of these features.

We will present multiple use-cases of HyperMapper highlighting the importance of design-space exploration. First, we will present a use-case of HyperMapper on the automatic tuning of hardware accelerators within the recently introduced Spatial programming language and compiler, minimizing design run-time under the constraint of the design fitting in a target FPGA. We will also present a use-case on HPVM, an intermediate parallel programming representation for performance portability to different hardware, minimizing both application performance and resource usage subject to the constraint of the design fitting in the target hardware.

Venue

Friday 02 Oct 2020, 11 am ET via Zoom

Organizers

Artur Souza

Universidade Federal de Minas Gerais

Luigi Nardi

Lund University

Stanford University

Matt Feldman

Stanford University

Kunle Olukotun

Stanford University

Invited Speakers

Adel Ejjeh - University of Illinois at Urbana-Champaign

HPVM-FPGA: Leveraging Compiler Optimizations for Hardware-Agnostic FPGA Programming

Program

Contact

Artur Souza: arturluis at dcc.ufmg.br

Luigi Nardi: luigi.nardi at cs.lth.se