Nayoung Kwon (undergraduate)  is majoring in electronic engineering at Kyungpook National University, Daegu, Korea . Her research interests include SoC Chip Design and Embeded System.

Pukyong National University, Pusan, Korea [Mar. 2019 ~ Feb. 2021] 

Kyungpook National University, Daegu, Korea [Mar. 2021 ~ Feb. 2023] 

Lightweight Buffer Insertion for Clock Tree Synthesis Visualization ICEIC 2022

Lightweighted CTS Preconstruction Techniques for Checking Clock Tree Synthesizable Paths in RTL Design Time, ISOCC 2022

Lightweighted CTS Preconstruction Techniques for Checking Clock Tree Synthesizable Paths in RTL Design Time (KCI), 2022

Lightweight Shallow CTS Techniques for Designing Clock Tree Synthesizable Verilog RTLs (SCI) (Under Revision) IEEE Access, 2023

Lightweighted Shallow CTS Techniques for Checking Clock Tree Synthesizable Paths and Optimizing Clock Tree in RTL Design Time (Under Review),  ICTC 2023

2021.07 - 2021.08 MIPS Processor Design by Matlab Simulink

2021.09 - 2021.12 Lightweight Buffer Insertion for Clock Tree Synthesis Visualization 

2022.01 - 2022.03 Qflow & Parser Verilog

2022.03 - 2022.08 Lightweighted CTS Preconstruction Techniques for Checking Clock Tree Synthesizable Paths in RTL Design Time 

2022.08 - 2023.02     Lightweighted Shallow CTS Techniques for Checking Clock Tree Synthesizable Paths in RTL Design Time 

 2023.03 - ing   Static timing analysis (STA) algorithm design...

 2023.06 - ing   Linux System programming ...