[1] A. Agarwal, A. M. Walke, N. Ronchi, M. I. Popovici, W. C. Y. Ma, C. J. Su, K. H. Kao, and J. V. Houdt, “Yttrium doped Hf0.5Zr0.5O2 based ferroelectric capacitor exhibiting fatigue free (>1012 Cycles), long retention, and imprint immune performance at 4 K,” IEEE Electron Device Lett., vol. 46, no. 7, pp. 1095-1098, Jul. 2025. DOI: 10.1109/LED.2025.3562798.
[2] William Cheng-Yu Ma*, Chun-Jung Su, Kuo-Hsing Kao, Yu-Chieh Yen, Ji-Min Yang, Yi-Han Li, Yen-Chen Chen, Jhe-Yu Lin, and Hui-Wen Chang, “Impact of pulse voltage stress on the reliability of ferroelectric thin-film transistor,” IEEE Trans. Device Mater. Rel., vol. 25, no. 2, pp. 240-246, Jun. 2025. DOI: 10.1109/TDMR.2025.3548038.
[3] Xin-Ren Yu, Jia Yuan Hung, Ta-Chun Cho, William Cheng-Yu Ma, Yao-Jen Lee, and Yeong-Her Wang, “Plasma-free nitridation for MOSCAPs and GeOI GAAFETs utilizing cyclic passivation of ozone/hydrazine with low leakage current, low interface traps, and high thermal stability,” IEEE Trans. Electron Devices, vol. 72, no. 4, pp. 1597-1603, Apr. 2025. DOI: 10.1109/TED.2025.3545401.
[4] William Cheng-Yu Ma*, Chun-Jung Su, Kuo-Hsing Kao, Yu-Chieh Yen, Ji-Min Yang, Yi-Han Li, Yen-Chen Chen, Jhe-Yu Lin, and Hui-Wen Chang, “High-performance junctionless ferroelectric thin-film transistor for low-voltage and high-speed nonvolatile memory applications,” IEEE Trans. Electron Devices, vol. 72, no. 1, pp. 247-252, Jan. 2025. DOI: 10.1109/TED.2024.3503539.
[5] Y.-C. Chen, J.-P. Chou, K.-C. Chen, J.-Y. Lin, W. C.-Y. Ma*, K.-H. Kao*, M.-H. Chiang, Y.-H. Wang, “Extracting device parameters of TFTs with ultrathin channels at low temperatures by particle swarm optimization,” IEEE Trans. Electron Devices, vol. 71, no. 8, pp. 4717-4722, Aug. 2024. DOI: 10.1109/TED.2024.3418934.
[6] William Cheng-Yu Ma*, Chun-Jung Su, Kuo-Hsing Kao, Ta-Chun Cho, Jing-Qiang Guo, Cheng-Jun Wu, Po-Ying Wu, and Jia-Yuan Hung, “Impact of dual-gate configuration on the endurance of ferroelectric thin-film transistors with nanosheet polycrystalline-silicon channel film,” ECS J. Solid State Sci. Technol., vol. 13, no. 4, pp. 045003, Apr. 2024. DOI: 10.1149/2162-8777/ad3c21.
[7] William Cheng-Yu Ma*, Chun-Jung Su, Kuo-Hsing Kao, Jing-Qiang Guo, Cheng-Jun Wu, Po-Ying Wu, and Jia-Yuan Hung, “Impact of nanosheet thickness on performance and reliability of polycrystalline-silicon thin-film transistors with double-gate operation,” IEEE Trans. Nanotechnol., vol. 22, pp. 740-746, Oct. 2023. DOI: 10.1109/TNANO.2023.3327087.
[8] William Cheng-Yu Ma*, Chun-Jung Su, Kuo-Hsing Kao, Yan-Qing Chen, Jing-Qiang Guo, Cheng-Jun Wu, Po-Ying Wu, and Jia-Yuan Hung, “Exploring performance and reliability behavior of nanosheet channel thin-film transistors under independent dual gate bias operation,” ECS J. Solid State Sci. Technol., vol. 12, no. 10, pp. 015004, Oct. 2023. DOI: 10.1149/2162-8777/ad017b.
[9] William Cheng-Yu Ma*, Chun-Jung Su, Kuo-Hsing Kao, Ta-Chun Cho, Jing-Qiang Guo, Cheng-Jun Wu, Po-Ying Wu, and Jia-Yuan Hung, “Ferroelectric tunnel thin-film transistor for synaptic applications,” ECS J. Solid State Sci. Technol., vol. 12, no. 5, pp. 055006, May 2023. DOI: 10.1149/2162-8777/acd212.
[10] Chia-Chuan Wu, William Cheng-Yu Ma*, Ting-Chang Chang*, Yu-Xuan Wang, Mao-Chou Tai, Yu-Fa Tu, Yu-An Chen, Hong-Yi Tu, Ya-Ting Chien, Han-Yu Chang, and Bo-Shen Huang, “Abnormal degradation behaviors under negative bias stress in flexible p-channel low-temperature polycrystalline silicon thin-film transistors after laser lift-off process,” IEEE Trans. Electron Devices, vol. 70, no. 3, pp. 1079-1084, Mar. 2023. DOI: 10.1109/TED.2023.3236914.
[11] William Cheng-Yu Ma*, Chun-Jung Su, Kuo-Hsing Kao, Yao-Jen Lee, Pin-Hua Wu, Hsin-Chun Tseng, Hsu-Tang Liao, Yu-Wen Chou, Min-Yu Chiu, and Yan-Qing Chen, “Impacts of pulse conditions on endurance behavior of ferroelectric thin-film transistor non-volatile memory,” Semicond. Sci. Technol., vol. 38, no. 3, pp. 035020, Mar. 2023. DOI: 10.1088/1361-6641/acb8d2.
[12] William Cheng-Yu Ma*, Chun-Jung Su, Kuo-Hsing Kao, Yao-Jen Lee, Ju-Heng Lin, Pin-Hua Wu, Jui-Che Chang, Cheng-Lun Yen, Hsin-Chun Tseng, Hsu-Tang Liao, Yu-Wen Chou, Min-Yu Chiu, and Yan-Qing Chen, “First demonstration of ferroelectric tunnel thin-film transistor non-volatile memory with polycrystalline-silicon channel and HfZrOx gate dielectric,” IEEE Trans. Electron Devices, vol. 69, no. 11, pp. 6072-6077, Nov. 2022. DOI: 10.1109/TED.2022.3208847.
[13] Shu-Wei Chang, Tsung-Han Lu, Cong-Yi Yang, Cheng-Jui Yeh, Min-Kun Huang, Ching-Fan Meng, Po-Jen Chen, Ting-Hsuan Chang, Yan-Shiuan Chang, Jhe-Wei Jhu, Tzu-Chieh Hong, Chu-Chu Ke, Xin-Ren Yu, Wen-Hsiang Lu, Mohammed Aftab Baig, Ta-Chun Cho, Po-Jung Sung, Chun-Jung Su, Fu-Kuo Hsueh, Bo-Yuan Chen, Hsin-Hui Hu, Chien-Ting Wu, Kun-Lin Lin, William Cheng-Yu Ma, Darsen D. Lu, Kuo-Hsing Kao, Yao-Jen Lee, Cheng-Li Lin, Kun-Ping Huang, Kun-Ming Chen, Yiming Li, Seiji Samukawa, Tien-Sheng Chao, Guo-Wei Huang, Wen-Fa Wu, Wen-Hsi Lee, Jiun-Yun Li, Jia-Min Shieh, Jenn-Hwan Tarng, Yeong-Her Wang, and Wen-Kuan Yeh, “First demonstration of heterogeneous IGZO/Si CFET monolithic 3-D integration with dual work function gate for ultralow-power SRAM and RF applications,” IEEE Trans. Electron Devices, vol. 69, no. 4, pp. 2101-2107, Apr. 2022. DOI: 10.1109/TED.2021.3138947.
[14] William Cheng-Yu Ma*, Chun-Jung Su, Yao-Jen Lee, Kuo-Hsing Kao, Ting-Hsuan Chang, Jui-Che Chang, Pin-Hua Wu, Cheng-Lun Yen, and Ju-Heng Lin, “Demonstration of synaptic characteristics of polycrystalline-silicon ferroelectric thin-film transistor for application of neuromorphic computing,” Semicond. Sci. Technol., vol. 37, no. 4, pp. 045003, Apr. 2022. DOI: 10.1088/1361-6641/ac51b6.
[15] William Cheng-Yu Ma* and Cai-Jia Tsai, “Impacts of independent dual-gate operation on reliability of nanosheet junctionless thin-film transistor,” IEEE Trans. Electron Devices, vol. 68, no. 12, pp. 6171-6176, Dec. 2021. DOI: 10.1109/TED.2021.3117901.
[16] William Cheng-Yu Ma*, Shen-Ming Luo, Cai-Jia Tsai, Jiun-Hung Lin, Ming-Jhe Li, Jhe-Wei Jhu, Ting-Hsuan Chang, Po-Jen Chen, and Yan-Shiuan Chang, “Impacts of ammonia gas plasma surface treatment on polycrystalline-silicon junctionless thin-film transistor,” IEEE Trans. Plasma Sci., vol. 49, no. 1, pp. 26-32, Jan. 2021. DOI: 10.1109/TPS.2020.3010483.
[17] William Cheng-Yu Ma*, Po-Jen Chen, Yan-Shiuan Chang, Jhe-Wei Jhu, and Ting-Hsuan Chang, “Impacts of O2 plasma on negative gate bias stress instability of tunnel thin-film transistor,” IEEE Trans. Plasma Sci., vol. 49, no. 1, pp. 15-20, Jan. 2021. DOI: 10.1109/TPS.2020.3015729.
[18] William Cheng-Yu Ma*, Hui-Shun Hsu, and Hsiao-Chun Wang, “Various reliability investigations of low temperature polycrystalline silicon tunnel field-effect thin-film transistor,” IEEE Trans. Device Mater. Rel., vol. 20, no. 4, pp. 775-780, Dec. 2020. DOI: 10.1109/TDMR.2020.3035336.
[19] William Cheng-Yu Ma* and Shen-Ming Luo, “Impacts of stress voltage and channel length on hot-carrier characteristics of tunnel field-effect thin-film transistor,” IEEE Trans. Electron Devices, vol. 67, no. 11, pp. 5243-5246, Nov. 2020. DOI: 10.1109/TED.2020.3025741.
[20] Kuo-Hsing Kao, Tzung Rang Wu, Hong-Lin Chen, Wen-Jay Lee, Nan-Yow Chen, William Cheng-Yu Ma, Chun-Jung Su, and Yao-Jen Lee, “Subthreshold swing saturation of nanoscale MOSFETs due to source-to-drain tunneling at cryogenic temperatures,” IEEE Electron Device Lett., vol. 41, no. 9, pp. 1296-1299, Sep. 2020. DOI: 10.1109/LED.2020.3012033.
[21] William Cheng-Yu Ma*, Yan-Jia Huang, Po-Jen Chen, Jhe-Wei Jhu, Yan-Shiuan Chang, and Ting-Hsuan Chang, “Impacts of vertically stacked monolithic 3D-IC process on characteristics of underlying thin-film transistor,” IEEE J. Electron Devices Soc., vol. 8, pp. 724-730, Jul. 2020. DOI: 10.1109/JEDS.2020.3009350.
[22] William Cheng-Yu Ma*, Ming-Jhe Li, Shen-Ming Luo, Jiun-Hung Lin, and Cai-Jia Tsai, “Gate capacitance effect on P-type tunnel thin-film transistor with TiN/HfZrO2 gate stack,” Thin Solid Films, vol. 697, pp. 137818, Mar. 2020. DOI: 10.1016/j.tsf.2020.137818.
[23] William Cheng-Yu Ma*, Jia-Yi Wang, Li-Wei Yu, Hsiao-Chun Wang, and Yan-Jia Huang, “Temperature dependence improvement of polycrystalline-silicon tunnel field-effect thin-film transistor,” Solid-State Electron., vol. 160, pp. 107621, Oct. 2019. DOI: 10.1016/j.sse.2019.107621.
[24] William Cheng-Yu Ma*, Hui-Shun Hsu, Chih-Cheng Fang, Che-Yu Jao, and Tzu-Han Liao, “Impacts of channel film thickness on poly-Si tunnel thin-film transistors,” Thin Solid Films, vol. 660, pp. 926-930, Aug. 2018. DOI: 10.1016/j.tsf.2018.02.026.
[25] William Cheng-Yu Ma*, Jia-Yi Wang, Hsiao-Chun Wang, Yan-Jia Huang, and Li-Wei Yu, “Dependence of sub-thermionic swing on channel thickness and drain bias of poly-Si junctionless thin-film transistor,” IEEE Electron Device Lett., vol. 39, no. 8, pp. 1122-1125, Aug. 2018. DOI: 10.1109/LED.2018.2850974.
[26] William Cheng-Yu Ma*, Hui-Shun Hsu, Chih-Cheng Fang, Che-Yu Jao, and Tzu-Han Liao, “Impacts of trap-state generation on tunnel thin-film transistor,” IEEE Trans. Electron Devices, vol. 65, no. 4, pp. 1363-1369, Apr. 2018. DOI: 10.1109/TED.2018.2801361.
[27] William Cheng-Yu Ma*, “Current degradation by carrier recombination in a poly-Si TFET with gate-drain underlapping,” IEEE Trans. Electron Devices, vol. 64, no. 3, pp. 1390-1393, Mar. 2017. DOI: 10.1109/TED.2017.2648846.
[28] William Cheng-Yu Ma*, Kang Chang, Yu-Cheng Lin, and Tai-Hsuan Wu, “Plasma induced interfacial layer impacts on TFETs with poly-Si channel Film by oxygen plasma surface treatment,” IEEE Trans. Plasma Sci., vol. 44, no. 12, pp. 3214-3218, Dec. 2016. DOI: 10.1109/TPS.2016.2621056.
[29] William Cheng-Yu Ma*, Zheng-Yi Lin, Yao-Sheng Huang, Bo-Siang Huang, and Zheng-Da Wu, “Positive bias temperature instability improvement of poly-Si thin-film transistor with HfO2 gate dielectric by ammonia plasma treatment,” IEEE Trans. Plasma Sci., vol. 44, no. 12, pp. 3153-3157, Dec. 2016. DOI: 10.1109/TPS.2016.2602380.
[30] William Cheng-Yu Ma*, Yi-Hsuan Chen, Zheng-Yi Lin, Yao-Sheng Huang, Bo-Siang Huang, and Zheng-Da Wu, “Performance improvement of poly-Si tunnel thin-film transistor by NH3 plasma treatment,” Thin Solid Films, vol. 618, pp. 178-183, Nov. 2016. DOI: 10.1016/j.tsf.2016.02.063.
[31] William Cheng-Yu Ma* and Yi-Hsuan Chen, “Performance improvement of poly-Si tunnel FETs by trap density reduction,” IEEE Trans. Electron Devices, vol. 63, no. 2, pp. 864-868, Feb. 2016. DOI: 10.1109/TED.2015.2505734.
[32] William Cheng-Yu Ma* and Chi-Yuan Huang, “Bias temperature instability comparison of CMOS LTPS-TFTs with HfO2 gate dielectric,” Solid-State Electron., vol. 114, no. 12, pp. 115-120, Dec. 2015. DOI: 10.1016/j.sse.2015.09.009.
[33] Yi-Hsuan Chen, William Cheng-Yu Ma, Jer-Yi Lin, Chun-Yen Lin, Po-Yang Hsu, Chi-Yuan Huang, and Tien-Sheng Chao*, “Impact of crystallization method on poly-Si tunnel FETs,” IEEE Electron Device Lett., vol. 36, no. 10, pp. 1060-1062, Oct. 2015. DOI: 10.1109/LED.2015.2468060.
[34] Yi-Hsuan Chen, William Cheng-Yu Ma*, and Tien-Sheng Chao, “High-performance poly-Si TFT with ultra-thin channel film and gate oxide for low-power application,” Semicond. Sci. Technol., vol. 30, no. 10, 105017, Oct. 2015. DOI:10.1088/0268-1242/30/10/105017.
[35] William Cheng-Yu Ma*, Sheng-Wei Yuan, Tsung-Chieh Chan, and Chi-Yuan Huang, “Threshold voltage reduction and mobility improvement of LTPS-TFTs with NH3 plasma treatment,” IEEE Trans. Plasma Sci., vol. 42, no. 12, pp. 3722-3725, Dec. 2014. DOI: 10.1109/TPS.2014.2352459.
[36] William Cheng-Yu Ma*, Chi-Yuan Huang, Tsung-Chieh Chan, and Sheng-Wei Yuan, “Reverse electrical behavior of n-channel and p-channel LTPS-TFTs by N2O plasma surface treatment,” IEEE Trans. Plasma Sci., vol. 42, no. 12, pp. 3825-3829, Dec. 2014. DOI: 10.1109/TPS.2014.2332187.
[37] William Cheng-Yu Ma*, “Distinction between interfacial layer effect and trap passivation effect of N2 plasma treatment on LTPS-TFTs,” Solid-State Electron., vol. 100, no. 10, pp. 45-48, Oct. 2014. DOI: 10.1016/j.sse.2014.07.005.
[38] William Cheng-Yu Ma*, “Asymmetric driving current modification of CMOS LTPS-TFTs with HfO2 gate dielectric,” IEEE Trans. Electron Devices, vol. 61, no. 3, pp. 930-932, Mar. 2014. DOI: 10.1109/TED.2014.2301992.
[39] William Cheng-Yu Ma*, T.-Y. Chiang, J.-W. Lin, and T.-S. Chao, “Oxide thinning and structure scaling down effect of low-temperature poly-Si thin-film transistors,” J. Display Technol., vol. 8, no. 1, pp. 12-17, Jan. 2012. DOI: 10.1109/JDT.2011.2162938.
[40] William Cheng-Yu Ma, T.-Y. Chiang, C.-R. Yeh, T.-S. Chao*, and T.-F. Lei, “Channel film thickness effect of low-temperature polycrystalline-silicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 58, no. 4, pp. 1268-1272, Apr. 2011. DOI: 10.1109/TED.2011.2104362.
[41] T.-Y. Chiang, William Cheng-Yu Ma, Y.-H. Wu, K.-T. Wang, and T.-S. Chao*, “A novel p-n-diode structure of SONOS-type TFT NVM with embedded silicon nanocrystals,” IEEE Electron Device Lett., vol. 31, no. 11, pp. 1239-1241, Nov. 2010. DOI: 10.1109/LED.2010.2064153.
[42] T. T.-J. Wang, William Cheng-Yu Ma, S.-W. Hung, and C.-T. Kuo*, “Low temperature Ni-nanocrystals-assisted hybrid polycrystalline silicon thin film transistor for non-volatile memory applications,” Thin Solid Films, vol. 518, no. 24, pp. 7429-7432, Oct. 2010. DOI: 10.1016/j.tsf.2010.05.010.
[43] T.-Y. Chiang, Y.-H. Wu, William Cheng-Yu Ma, P.-Y. Kuo, K.-T. Wang, C.-C. Liao, C.-R. Yeh, W.-L. Yang, and T.-S. Chao*, “Characteristics of SONOS-type flash memory with in-situ embedded silicon nanocrystals,” IEEE Trans. Electron Devices, vol. 57, no. 8, pp. 1895-1902, Aug. 2010. DOI: 10.1109/TED.2010.2051489.
[44] T. T.-J. Wang*, P.-L. Gao, William Cheng-Yu Ma, and C.-T. Kuo, “Low-temperature polycrystalline silicon thin film transistor nonvolatile memory using Ni nanocrystals as charge-trapping centers fabricated by hydrogen plasma process,” Jpn. J. Appl. Phys., vol. 49, no. 6, pp. 06GG151-06GG154, Jun. 2010. DOI: 10.1143/JJAP.49.06GG15.
[45] T.-Y. Chiang, Ming-Wen Ma, Y.-H. Wu, P.-Y. Kuo, K.-T. Wang, C.-C. Liao, C.-R. Yeh, and T.-S. Chao-, “MILC-TFT with high-k dielectrics for one-time-programmable memory application,” IEEE Electron Device Lett., vol. 30, no. 9, pp. 954-956, Sep. 2009. DOI: 10.1109/LED.2009.2027035.
[46] Ming-Wen Ma, T.-Y. Chiang, C.-R. Yeh, T.-S. Chao*, and T.-F. Lei, “Electrical characteristics of high performance SPC and MILC p-channel LTPS-TFT with high-k gate dielectric,” Electrochem. and Solid State Lett., vol. 12, no. 10, pp. H361-H364, Jul. 2009. DOI: 10.1149/1.3177277.
[47] Ming-Wen Ma, T.-Y. Chiang, T.-S. Chao*, and T.-F. Lei, “High-performance p-channel LTPS-TFT using HfO2 gate dielectric and nitrogen ion implantation,” Semicond. Sci. Technol., vol. 24, no. 7, pp. 072001, Jul. 2009. DOI: 10.1088/0268-1242/24/7/072001.
[48] Ming-Wen Ma, T.-Y. Chiang, W.-C. Wu, T.-S. Chao*, and T.-F. Lei, “Characteristics of HfO2/poly-Si interfacial layer on CMOS LTPS-TFTs with HfO2 gate dielectric and O2 plasma surface treatment,” IEEE Trans. Electron Devices, vol. 55, no. 12, pp. 3489-3493, Dec. 2008. DOI: 10.1109/TED.2008.2006543.
[49] W.-C. Wu, T.-S. Chao*, T.-H. Chiu, J.-C. Wang, C.-S. Lai, Ming-Wen Ma, and W.-C. Lo, “Positive bias temperature instability (PBTI) characteristics of contact-etch-stop-layer-induced local-tensile-strained HfO2 nMOSFET,” IEEE Electron Device Lett., vol. 29, no. 12, pp. 1340-1343, Dec. 2008. DOI: 10.1109/LED.2008.2005519.
[50] Ming-Wen Ma, T.-S. Chao*, T.-Y. Chiang, W.-C. Wu, and T.-F. Lei, “Impacts of N2 and NH3 plasma surface-treatment on high performance LTPS-TFT with high-k gate dielectric,” IEEE Electron Device Lett., vol. 29, no. 11, pp. 1236-1238, Nov. 2008. DOI: 10.1109/LED.2008.2004781.
[51] K.-H. Kao, S.-H. Chuang, W.-C. Wu, T.-S. Chao*, J.-H. Chen, Ming-Wen Ma, R.-H. Gao, and M. Y. Chiang, “X-ray photoelectron spectroscopy energy band alignment of spin-on CoTiO3 high-k dielectric prepared by sol-gel spin coating method,” Appl. Phys. Lett., vol. 93, no. 9, pp. 092907, Sep. 2008. DOI: 10.1063/1.2978231.
[52] W.-C. Wu, T.-S. Chao*, T.-H. Chiu, J.-C. Wang, C.-S. Lai, Ming-Wen Ma, and W.-C. Lo, “Performance and Interface Characterization for contact etch stop layer–strained nMOSFET with HfO2 gate dielectrics under pulsed-IV measurement,” Electrochem. Solid-State Lett., vol. 11, no. 8, pp. H230-H232, Aug. 2008. DOI: 10.1149/1.2938021.
[53] W. C. Wu, C.-S. Lai, T.-M. Wang, J.-C. Wang, C. W. Hsu, Ming Wen Ma, W.-C. Lo, and T. S. Chao*, “Carrier transportation mechanism of the TaN/HfO2/IL/Si structure with silicon surface fluorine implantation,” IEEE Trans. Electron Devices, vol. 55, no. 7, pp. 1639-1646, Jul. 2008. DOI: 10.1109/FED.2008.925150.
[54] Ming-Wen Ma, T.-S. Chao*, C.-J. Su, W.-C. Wu, K.-H. Kao, and T.-F. Lei, “High performance metal-induced laterally crystallized polycrystalline silicon p-channel thin-film transistor with TaN/HfO2 gate stack structure,” IEEE Electron Device Lett., vol. 29, no. 6, pp. 592-594, Jun. 2008. DOI: 10.1109/LED.2008.921208.
[55] Ming-Wen Ma, C.-Y. Chen, C.-J. Su, W.-C. Wu, K.-H. Kao, T.-S. Chao*, and T.-F. Lei, “Reliability mechanisms of LTPS-TFT with HfO2 gate dielectric: PBTI, NBTI and hot carrier stress,” IEEE Trans. Electron Devices, vol. 55, no. 5, pp. 1153-1160, May 2008. DOI: 10.1109/TED.2008.919710.
[56] Ming-Wen Ma, C.-Y. Chen, C.-J. Su, W.-C. Wu, T.-Y. Yang, K.-H. Kao, T.-S. Chao*, and T.-F. Lei, “Improvement on performance and reliability of TaN/HfO2 LTPS-TFTs with fluorine implantation,” Solid-State Electronics, vol. 52, no. 3, pp. 342-347, Mar. 2008. DOI: 10.1016/j.sse.2007.07.018.
[57] C.-Y. Chen*, Ming-Wen Ma, W.-C. Chen, H.-Y. Lin, K.-L. Yeh, S.-D. Wang, and T.-F. Lei, “Analysis of negative bias temperature instability in body-tied low-temperature polycrystalline silicon thin-film transistors,” IEEE Electron Device Lett., vol. 29, no. 2, pp. 165-167, Feb. 2008. DOI: 10.1109/LED.2007.914083.
[58] Ming-Wen Ma, C.-Y. Chen, C.-J. Su, W.-C. Wu, Y.-H. Wu, K.-H. Kao, T.-S. Chao*, and T.-F. Lei, “Characteristics of PBTI and hot carrier stress for LTPS-TFT with high-k gate dielectric,” IEEE Electron Device Lett., vol. 29, no. 2, pp. 171-173, Feb. 2008. DOI: 10.1109/LED.2007.914091.
[59] Ming-Wen Ma, C.-Y. Chen, C.-J. Su, W.-C. Wu, Y.-H. Wu, T.-Y. Yang, K.-H. Kao, T.-S. Chao*, and T.-F. Lei, “Impacts of fluorine ion implantation with low-temperature solid-phase crystallized activation on high-k LTPS-TFT,” IEEE Electron Device Lett., vol. 29, no. 2, pp. 168-170, Feb., 2008. DOI: 10.1109/LED.2007.914071.
[60] W. C. Wu, C. S. Lai*, T. M. Wang, J. C. Wang, C. W. Hsu, Ming Wen Ma, and T. S. Chao, “Current transport mechanism for HfO2 gate dielectrics with fluorine incorporation,” Electrochem. Solid-State Lett., vol. 11, no. 1, pp. H15-H18, Jan. 2008. DOI: 10.1149/1.2805079.
[61] W.-C. Wu, T.-S. Chao*, W.-C. Peng, W.-L. Yang, J.-H. Chen, Ming-Wen Ma, C.-S. Lai, T.-Y. Yang, C.-H. Lee, T.-M. Hsieh, J. C. Liou, T. P. Chen, C. H. Chen, C. H. Lin, H. H. Chen, and Joe Ko, “Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory,” Semicond. Sci. Technol., vol. 23, no. 1, pp. 015004, Jan. 2008. DOI: 10.1088/0268-1242/23/1/015004.
[62] J.-H. Chen, T.-F. Lei, Dolf Landheer, Xiaohua Wu, Ming-Wen Ma, W.-C. Wu, T.-Y. Yang, and T.-S. Chao*, “Nonvolatile memory characteristics with embedded hemispherical silicon nanocrystals,” Jpn. J. Appl. Phys., vol. 46, no. 10A, pp. 6586-6588, Oct. 2007. DOI: 10.1143/JJAP.46.6586.
[63] C.-Y. Chen*, J.-W. Lee, Ming-Wen Ma, W.-C. Chen, H.-Y. Lin, K.-L. Yeh, S.-D. Wang, and T.-F. Lei, “Bias temperature instabilities for low-temperature polycrystalline silicon complementary thin-film transistors,” J. Electrochem. Soc., vol. 154, no. 8, pp. H704-H707, Jun. 2007. DOI: 10.1149/1.2742810.
[64] W. C. Wu, C. S. Lai, J. C. Wang, J. H. Chen, Ming Wen Ma, and T. S. Chao*, “High-performance HfO2 gate dielectrics fluorinated by postdeposition CF4 plasma treatment,” J. Electrochem. Soc., vol. 154, no. 7, pp. H561-H565, May 2007. DOI: 10.1149/1.2733873.
[65] C.-Y. Chen*, J.-W. Lee, P.-H. Lee, W.-C. Chen, H.-Y. Lin, K.-L. Yeh, Ming-Wen Ma, S.-D. Wang, and T.-F. Lei, “A reliability model for low-temperature polycrystalline silicon thin-film transistors,” IEEE Electron Device Lett., vol. 28, no. 5, pp. 392-394, May 2007. DOI: 10.1109/LED.2007.895454.
[66] Ming-Wen Ma, C.-H. Wu, T.-Y. Yang, K.-H. Kao, W.-C. Wu, T.-S. Chao*, and T.-F. Lei, “Impact of high-k offset spacer in 65-nm node SOI devices,” IEEE Electron Device Lett., vol. 28, no. 3, pp. 238-241, Mar. 2007. DOI: 10.1109/LED.2007.891282.
[67] Ming-Wen Ma, T.-S. Chao*, K.-H. Kao, J.-S. Huang, and T.-F. Lei, “High-k material sidewall with source/drain-to-gate non-overlapped structure for low standby power applications,” Jpn. J. Appl. Phys., vol. 45, no. 11, pp. 8656-8658, Nov. 2006. DOI: 10.1143/JJAP.45.8656.
[68] Ming-Wen Ma, T.-S. Chao*, K.-H. Kao, J.-S. Huang, and T.-F. Lei, “Fringing electric field effect on 65-nm-node fully depleted silicon-on-insulator devices,” Jpn. J. Appl. Phys., vol. 45, no. 9A, pp. 6854-6859, Sep. 2006. DOI: 10.1143/JJAP.45.6854.
[1] H. T. Liao, M. K. Huang, H. Y. Chang, K. H. Kao, W. C. Y. Ma, Y. H. Wang, C. J. Su, “Investigation of Top-gate MoS2 FETs with NH3-treated Interface,” in IEDMS2023, pp. #1288, Kaohsiung, Taiwan, Oct. 2023.
[2] William Cheng-Yu Ma, Jing-Qiang Guo, Cheng-Jun Wu, Po-Ying Wu, Jia-Yuan Hung, Yen-Chen Chen, Yi-Han Li, Ji-Min Yang, Yu-Chieh Yen, “Assessing the Gate-Bias Stress Instability of Double-Gate versus Single-Gate Operations in Polycrystalline-Silicon Nanosheet Transistors,” in IEDMS2023, pp. #1066, Kaohsiung, Taiwan, Oct. 2023.
[3] William Cheng-Yu Ma, Jing-Qiang Guo, Cheng-Jun Wu, Po-Ying Wu, Jia-Yuan Hung, Yen-Chen Chen, Yi-Han Li, Ji-Min Yang, Yu-Chieh Yen, “Exploring the Trade-off Between Performance Enhancement and Reliability Degradation in Nanosheet-structured Polycrystalline-silicon Thin Film Transistors,” in IEDMS2023, pp. #1068, Kaohsiung, Taiwan, Oct. 2023.
[4] W.-C. Lin, H.-P. Huang, K.-H. Kao, M.-H. Chiang, D. Lu, W.-C. Hsu, Y.-H. Wang, W.C.-Y. Ma, H.-H. Tsai, Y.-J. Lee, H.-L. Chiang, J.-F. Wang, and I. Radu, “MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization,” in Proc. IEEE ESSDERC, pp. 9-12, Lisbon, Portugal, Sep. 2023. DOI: 10.1109/ESSDERC59256.2023.10268514.
[5] Min-Kun Huang, Hsu-Tang Liao, William Cheng-Yu Ma, Yeong-Her Wang, and Chun-Jung Su, “Investigation of Top-gate MoS2 FETs by Low-temperature ALD High-κ and Hydrazine Passivated Interface,” in 2023 International Conference on Solid State Devices and Materials (SSDM), pp. PS-8-12, Nagoya, Japan, Sep. 2023.
[6] William Cheng-Yu Ma, Chun-Jung Su, Kuo-Hsing Kao, Ta-Chun Cho, Jing-Qiang Guo, Cheng-Jun Wu, Po-Ying Wu, and Jia-Yuan Hung, “Insights of Nanosheet Channel Thickness on Reliability Degradation of Thin-Film Transistor,” 2023 30th International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD), pp. 126-128, Kyoto, Japan, Jul. 2023.
[7] William Cheng-Yu Ma, Chun-Jung Su, Kuo-Hsing Kao, Ta-Chun Cho, Jing-Qiang Guo, Cheng-Jun Wu, Po-Ying Wu, and Jia-Yuan Hung, “Impacts of Asymmetry Double Gate Structure on Reliability Degradation of Thin-Film Transistor With Nanosheet Channel,” 2023 30th International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD), pp. 129-131, Kyoto, Japan, Jul. 2023.
[8] William Cheng-Yu Ma, Chun-Jung Su, Kuo-Hsing Kao, Ta-Chun Cho, Jing-Qiang Guo, Cheng-Jun Wu, Po-Ying Wu, and Jia-Yuan Hung, “Tunnel Thin-Film Transistor Featuring Ferroelectric Gate Stack for Synaptic Applications,” 2023 30th International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD), pp. 154-156, Kyoto, Japan, Jul. 2023.
[9] X.-R. Yu, M.-H. Chuang, S.-W. Chang, W.-H. Chang, T.-C. Hong, C.-H. Chiang, W.-H. Lu, C.-Y. Yang, W.-J. Chen, J.-H. Lin, P.-H. Wu, T.-C. Sun, S. Kola, Y.-S. Yang, Yun Da, P.-J. Sung, C.-T. Wu, T.-C. Cho, G.-L. Luo, K.-H. Kao, M.-H. Chiang, W. C.-Y. Ma, C.-J. Su, T.-S. Chao, T. Maeda, S. Samukawa, Y. Li, Y.-J. Lee, W.-F. Wu, J.-H. Tarng, and Y.-H. Wang, “Integration design and process of 3-D heterogeneous 6T SRAM with double layer transferred Ge/2Si CFET and IGZO pass gates for 42% reduced cell size,” in Proc. IEEE IEDM, pp. 20.5.1-20.5.4, Dec. 2022. DOI: 10.1109/IEDM45625.2022.10019507.
[10] Chia-Chuan Wu, William Cheng-Yu Ma, Yu-Xuan Wang, Mao-Chou Tai, Yu-An Chen, Hong-Yi Tu, Sheng-Yao Chou, Ya-Ting Chien, Ting-Chang Chang, “Investigation of electrical characteristics in low-temperature polycrystalline silicon thin-film transistors fabricated at low-temperature process,” in 2022 IET International Conference on Engineering Technologies and Applications (IET-ICETA), pp. 1-2, Oct. 2022. DOI: 10.1109/IET-ICETA56553.2022.9971607.
[11] X.-R. Yu, W.-H Chang, T.-C. Hong, P.-J. Sung, A. Agarwal, G.-L. Luo, C.-T. Wu, K.-H. Kao, C.-J. Su, S.-W. Chang, W.-H. Lu, P.-Y. Fu, J.-H. Lin, P.-H. Wu, T.-C. Cho, W. C.-Yu. Ma, D.-D. Lu, T.-S. Chao, T. Maeda, Y.-J. Lee, W.-F. Wu, and W.-K. Yeh, “First demonstration of vertical stacked hetero-oriented n-Ge (111)/p-Ge (100) CFET toward mobility balance engineering,” in Proc. Symp. VLSI Technol., pp. 399-400, Jun. 2022. DOI: 10.1109/VLSITechnologyandCir46769.2022.9830316.
[12] S.-W.Chang, T.-H. Lu, C.-Y. Yang, C.-J. Yeh, M.-K. Huang, C.-F. Meng, P.-J. Chen, T.-H. Chang, Y.-S. Chang, J.-W. Jhu, T.-Z. Hong, C.-C. Ke, X.-R. Yu, W.-H. Lu, M. A. Baig, T.-C. Cho, P.-J. Sung, C.-J. Su, F.-K. Hsueh, B.-Y. Chen, H.-H. Hu, C.-T. Wu, K.-L. Lin, W. C.-Y. Ma, D.-D. Lu, K.-H. Kao, Y.-J. Lee, C.-L. Lin, K.-P. Huang, K.-M. Chen, Y. Li, S. Samukawa, T.-S. Chao, G.-W. Huang, W.-F. Wu, W.-H. Lee, J.-Y. Li, J.-M. Shieh, J.-H. Tarng, Y.-H. Wang, and W.-K. Yeh, “First demonstration of heterogeneous IGZO/Si CFET monolithic 3D integration with dual workfunction gate for ultra low-power SRAM and RF applications,” in Proc. IEEE IEDM, pp. 34.4.1-34.4.4, Dec. 2021. DOI: 10.1109/IEDM19574.2021.9720675.
[13] Jui-Che Chang, Pin-Hua Wu, Cheng-Lun Yen, Ju-Heng Lin, Hsin-Chun Tseng, Min-Yu Chiu, Hsu-Tang Liao, Yan-Qing Chen, Yu-Wen Chou, William Cheng-Yu Ma, “Impacts of nitrogen plasma surface treatment on the memory window of ferroelectric memory,” 12th Asia-Pacific International Symposium on the Basics and Applications of Plasma Technology (APSPT-12), Taipei, Taiwan, P-16, Dec. 2021.
[14] Jui-Che Chang, Pin-Hua Wu, Cheng-Lun Yen, Ju-Heng Lin, Hsin-Chun Tseng, Min-Yu Chiu, Hsu-Tang Liao, Yan-Qing Chen, Yu-Wen Chou, William Cheng-Yu Ma, “Improvement of dynamic stress effect of the tunnel thin-film transistor by O2 plasma,” 12th Asia-Pacific International Symposium on the Basics and Applications of Plasma Technology (APSPT-12), Taipei, Taiwan, P-17, Dec. 2021.
[15] Jui-Che Chang, Pin-Hua Wu, Cheng-Lun Yen, Ju-Heng Lin, Hsu-Tang Liao, Hsin-Chun Tseng, Min-Yu Chiu, Yan-Qing Chen, Yu-Wen Chou, William Cheng-Yu Ma, “Demonstration of ferroelectric tunnel thin-film transistor with HfZrOx gate dielectric for application of synaptic device,” TACT2021 International Thin Films Conference, Taipei, Taiwan, C-P-303, Nov. 2021.
[16] T.-Z. Hong, W.-H. Chang, A. Agarwal, Y.-T. Huang, C.-Y. Yang, T.-Y. Chu, H.-Y. Chao, Y. Chuang, S.-T. Chung, J.-H. Lin, S.-M. Luo, C.-J. Tsai, M.-J. Li, X.-R. Yu, N.-C. Lin, T.-C. Cho, P.-J. Sung, C.-J. Su, G.-L. Luo, F.-K. Hsueh, K.-L. Lin, H. Ishii, T. Irisawa, T. Maeda, C.-T. Wu, W. C.-Y. Ma, D.-D. Lu, K.-H. Kao, Y.-J. Lee, H. J.-H. Chen, C.-L. Lin, R. W. Chuang, K.-P. Huang, S. Samukawa, Y.-M. Li, J.-H. Tarng, T.-S. Chao, M. Miura, G.-W. Huang, W.-F. Wu, J.-Y. Li, J.-M. Shieh, Y.-H. Wang, and W.-K. Yeh, “First demonstration of heterogeneous complementary FETs utilizing low-temperature (200 °C) hetero-layers bonding technique (LT-HBT),” in Proc. IEEE IEDM, pp. 15.5.1-15.5.4, Dec. 2020.
[17] S.-W. Chang, P.-J. Sung, T-Y. Chu, D. D. Lu, C. -J. Wang, N.-C. Lin, C.-J. Su, S.-H. Lo, H.-F. Huang, J.-H. Li, M.-K. Huang, Y.-C. Huang, S.-T. Huang, H.-C. Wang, Y.-J. Huang, J.-Y. Wang, L.-W Yu, Y.-F. Huang, F.-K. Hsueh, C.-T. Wu, W. C.-Y. Ma, K.-H. Kao, Y.-J. Lee, C.-L. Lin, R.W. Chuang, K.-P. Huang, S. Samukawa, Y. Li, W.-H. Lee, T.-S. Chao, G.-W. Huang, W.-F. Wu, J.-Y. Li, J.-M. Shieh, W. -K. Yeh, and Y.-H. Wang, “First demonstration of CMOS inverter and 6T-SRAM based on GAA CFETs structure for 3D-IC applications,” in Proc. IEEE IEDM, pp. 11.7.1-11.7.4, Dec. 2019. Doi: 10.1109/IEDM19573.2019.8993525.
[18] William Cheng-Yu Ma*, Yan-Shiuan Chang, Po-Jen Chen, Jhe-Wei Jhu, and Ting-Hsuan Chang, “Impacts of ammonia gas plasma surface treatment on junctionless polycrystalline-silicon thin-film transistor,” The 11th Asia-Pacific International Symposium on the Basics and Applications of Plasma Technology (APSPT-11), Kanazawa, Japan, P2-36, Dec. 2019.
[19] William Cheng-Yu Ma*, Po-Jen Chen, Yan-Shiuan Chang, Jhe-Wei Jhu, and Ting-Hsuan Chang, “Impacts of O2 plasma on negative gate bias stress instability of tunnel thin-film transistor,” The 11th Asia-Pacific International Symposium on the Basics and Applications of Plasma Technology (APSPT-11), Kanazawa, Japan, P2-37, Dec. 2019.
[20] Jiun-Hung Lin, Ming-Jhe Li, Shen-Ming Luo, Cai-Jia Tsai, and William Cheng-Yu Ma*, “Demonstration of vertically integrated complementary thin-film transistor inverter with nanosheet channel film,” TACT2019 International Thin Films Conference, Taipei, Taiwan, C-P-562, Nov. 2019.
[21] Cai-Jia Tsai, Shen-Ming Luo, Ming-Jhe Li, Jiun-Hung Lin, and William Cheng-Yu Ma*, “Hot carrier stress characterization of tunnel thin-film transistor,” TACT2019 International Thin Films Conference, Taipei, Taiwan, C-P-486, Nov. 2019.
[22] Shen-Ming Luo, Ming-Jhe Li, Jiun-Hung Lin, Cai-Jia Tsai, and William Cheng-Yu Ma*, “Impacts of operation mode on polycrystalline-silicon nanosheet thin-film transistor with double gate structure,” TACT2019 International Thin Films Conference, Taipei, Taiwan, C-P-281, Nov. 2019.
[23] Ming-Jhe Li, Shen-Ming Luo, Jiun-Hung Lin, Cai-Jia Tsai, and William Cheng-Yu Ma*, “High performance p-channel tunnel thin-film transistor with TiN/HfZrO gate stack,” TACT2019 International Thin Films Conference, Taipei, Taiwan, C-P-250, Nov. 2019.
[24] P.-J. Sung, C.-J. Su, D. D. Lu, S.-X. Luo, K.-H. Kao, J.-Y. Ciou, C.-Y. Jao, H.-S. Hsu, C.-J. Wang, T.-C. Hong, T.-H. Liao, C.-C. Fang, Y.-S. Wang, H.-F. Huang, J.-H. Li, Y.-C. Huang, F.-K. Hsueh, C.-T. Wu, Y.-C. Huang, W. C.-Y. Ma, K.-P. Huang, Y.-J. Lee, T.-S. Chao, J.-Y. Li, W.-F. Wu, W.-K. Yeh, and Y.-H. Wang, “Fabrication of Ω-gated negative capacitance FinFETs and SRAM,” IEEE VLSI-TSA, Hsinchu, Taiwan, pp. 1-2, Apr. 2019.
[25] William Cheng-Yu Ma*, Hsiao-Chun Wang, Li-Wei Yu, Jia-Yi Wang, Yan-Jia Huang, Ming-Jhe Li, Shen-Ming Luo, Cai-Jia Tsai, and Jiun-Hung Lin, “PON body effect on junctionless thin-film transistor,” The 15th International Thin-Film Transistor Conference (ITC 2019), Okinawa, Japan, pp. 58-59, Feb. 2019.
[26] P.-J. Sung, C.-Y. Chang, L.-Y. Chen, K.-H. Kao, C.-J. Su, T.-H. Liao, C.-C. Fang, C.-J. Wang, T.-C. Hong, C.-Y. Jao, H.-S. Hsu, S.-X. Luo, Y.-S. Wang, H.-F. Huang, J.-H. Li, Y.-C. Huang, F.-K. Hsueh, C.-T. Wu, Y.-M. Huang, F.-J. Hou, G.-L. Luo, Y.-C. Huang, Y.-L. Shen, W. C.-Y. Ma, K.-P. Huang, K.-L. Lin, S. Samukawa, Y. Li, G.-W Huang, Y.-J. Lee*, J.-Y. Li, W.-F. Wu, J.-M. Shieh, T.-S. Chao, W. -K. Yeh, Y.-H. Wang, “Voltage transfer characteristic matching by different nanosheet layer numbers of vertically stacked junctionless CMOS inverter for SoP/3D-ICs applications,” in Proc. IEEE IEDM, Dec. 2018, pp. 21.4.1-21.4.4.
[27] William Cheng-Yu Ma*, Hsiao-Chun Wang, Yan-Jia Huang, Le-Wei Yu, and Jia-Yi Wang, “Impacts of Interface Trap State Density on the Tunnel Field-Effect Transistor,” International Congress on Engineering and Information (ICEAI 2018), May, Hokkaido, Japan, pp.134, May 2018.
[28] Tzu-Han Liao*, Che-Yu Jao, Hui-Shun Hsu, Chih-Cheng Fang, William Cheng-Yu Ma, “Gate oxide thickness effect on tunnel transistor with poly-Si channel film,” TACT2017 International Thin Films Conference, Hualien, Taiwan, C-P-436, Oct. 2017.
[29] Hui-Shun Hsu*, Che-Yu Jao, Tzu-Han Liao, Chih-Cheng Fang, William Cheng-Yu Ma, “Impacts of channel film thickness on poly-Si tunnel thin-film transistors,” TACT2017 International Thin Films Conference, Hualien, Taiwan, C-P-275, Oct. 2017.
[30] Chih-Cheng Fang*, Hui-Shun Hsu, Che-Yu Jao, Tzu-Han Liao, William Cheng-Yu Ma, “Improvement of drain underlapping effect on poly-Si tunnel thin-film transistor by trap passivation,” TACT2017 International Thin Films Conference, Hualien, Taiwan, C-P-235, Oct. 2017.
[31] William Cheng‐Yu Ma*, Hui‐Shun Hsu, Che‐Yu Jao, Chih‐Cheng Fang and Tzu‐Han Liao, “Positive bias temperature instability of tunnel thin-film transistor for applications of system-on-panel and three-dimension integrated circuits” Silicon Nanoelectronics Workshop (SNW2017), Kyoto, Japan, pp. 125-126, Jun. 2017.
[32] Ruei-Jen Wu* and William Cheng-Yu Ma, “Characterization of poly-Si tunnel field-effect transistors with different source/drain structures,” 2016 International Electron Devices and Materials Symposium (IEDMS 2016), Taipei, Taiwan, #1230, Nov. 2016.
[33] William Cheng-Yu Ma*, Bo-Siang Huang, Yao-Sheng Huang, and Zheng-Da Wu, “Interface trap reduction impacts on tunnel field-effect transistor by oxygen plasma,” APSPT-9/SPSM-28, Nagasaki, Japan, P1-5, Dec. 2015.
[34] William Cheng-Yu Ma*, Yao-Sheng Huang, Bo-Siang Huang, and Zheng-Da Wu, “Temperature effect and reliability improvement of Thin-Film transistor by plasma treatment,” APSPT-9/SPSM-28, Nagasaki, Japan, P1-1, Dec. 2015.
[35] William Cheng-Yu Ma*, Meng-Chien Lee, Chi-Yuan Huang, “Bi-layer dielectric structure of IGZO thin-film transistor for gate stack and passivation layer application,” 2015 International Thin Films Conference (TACT2015), Tainan, Taiwan, 454, Nov. 2015.
[36] Chi-Yuan Huang, Meng-Chien Lee, Yi-Hsuan Chen, William Cheng-Yu Ma*, “Performance improvement of poly-Si tunnel thin-film transistor by trap passivation,” 2015 International Thin Films Conference (TACT2015), Tainan, Taiwan, 484, Nov. 2015.
[37] William Cheng-Yu Ma* and Chi-Yuan Huang, “Performance improvement of LTPS-TFTs with various plasma surface treatment,” ISPlasma2015/IC-PLANTS2015, Nagoya, Japan, A4-P-07, Mar. 2015.
[38] William Cheng-Yu Ma* and Y.-H. Chen, “BTI comparison of CMOS LTPS-TFTs with high-κ gate dielectric,” 2014 International Electron Devices and Materials Symposium (IEDMS 2014), Hualien, Taiwan, #1230, Nov. 2014.
[39] William Cheng-Yu Ma*, “Threshold voltage reduction and mobility improvement of LTPS-TFTs by N2 plasma nitridation,” The 8th Asia-Pacific International Symposium on the Basics and Applications of Plasma Technology (APSPT-8), Hsinchu, Taiwan, pp. 46, Dec. 2013.
[40] William Cheng-Yu Ma*, “Surface roughness scattering improvement of LTPS-TFTs by O2 plasma oxidation,” The 8th Asia-Pacific International Symposium on the Basics and Applications of Plasma Technology (APSPT-8), Hsinchu, Taiwan, pp. 163, Dec. 2013.
[41] W.-H. Hung, Y.-K. Fang, William Cheng-Yu Ma, T.-F. Chen, T.-M. Cheng, and F.-R. Juang, “The lanthanum oxide capping layer induced flat-band roll-off behaviors in high-k/metal-gate NMOSFETs with 28nm CMOS technology,” IEEE International NanoElectronics Conference (INEC), Tao-Yuan, Taiwan, pp. 1-2, Jun. 2011.
[42] W.-C. Wu, C.-S. Lai, S.-C. Lee, Ming-Wen Ma, T.-S. Chao, J.-C. Wang, C.-W. Hsu, P.-C. Chou, J.-H. Chen, K.-H. Kao, W.-C. Lo, T.-Y. Lu, L.-L. Tay, and N. Rowell, “Fluorinated HfO2 gate dielectrics engineering for CMOS by pre- and post-CF4 plasma passivation,” IEEE International Electron Devices Meeting (IEDM), San Francisco, California, pp. 1-4, Dec. 2008.
[43] W.-C. Wu, T.-S. Chao, T.-H. Chiu, J.-C. Wang, C.-S. Lai, Ming-Wen Ma, W.-C. Lo, and Y.-H. Ho, “Performance enhancement for strained HfO2 nMOSFET with contact etch stop Layer (CESL) under pulsed-IV measurement,” IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Tainan, Taiwan, pp. 161-164, Dec. 2007.
[44] C.-Y. Chen, Ming-Wen Ma, W.-C. Chen, H.-Y. Lin, K.-L. Yeh, S.-D. Wang, and T.-F. Lei, “NBTI-stress induced grain-boundary degradation in low-temperature poly-Si thin-film transistors,” International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, pp. 438-439, Sep. 2007.
[45] W. C. Wu, C. S. Lai, T. M. Wang, J. C. Wang, Ming Wen Ma, and T. S. Chao, “Current transportation mechanism of HfO2 gate dielectrics with silicon surface fluorine implantation (SSFI) in CMOS Application,” International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, pp. 408-409, Sep. 2007.
[46] W.-C. Wu, T.-S. Chao, W.-C. Peng, W.-L. Yang, J.-C. Wang, J.-H. Chen, Ming-Wen Ma, C.-S. Lai, T.-Y. Yang, T.-P. Chen, C.-H. Chen, C.-H. Lin, H.-H. Chen, and Joe Ko, “A highly reliable multi-level and 2-bit/cell operation of wrapped-select-gate (WSG) SONOS memory with optimized ONO thickness,” VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, pp. 1-2, Apr. 2007.
[47] C.-Y. Chen, T.-Y. Wang, Ming-Wen Ma, W.-C. Chen, H.-Y. Lin, K.-L. Yeh, S.-D. Wang, and T.-F. Lei, “Dynamic negative bias temperature instability in low-temperature poly-Si thin-film transistors,” International Asia Display Conference, Shanghai, China, pp. 1233-1237, Mar. 2007.
[48] Ming-Wen Ma*, T.-Y. Yang, K.-H. Kao, C.-J. Su, C.-Y. Chen, T.-S. Chao, and T.-F. Lei, “Mobility improvement of HfO2 LTPS-TFTs with nitrogen implantation,” International Asia Display Conference (AD), Shanghai, China, pp. 674-677, Mar. 2007.
[49] T.-Y. Yang, Ming-Wen Ma*, K.-H. Kao, C.-J. Su, T.-S. Chao, and T.-F. Lei, “Impacts of nitric acid oxidation on low-temperature polycrystalline silicon TFTs with high-k gate dielectric,” International Asia Display Conference, Shanghai, China, pp. 519-522, Mar. 2007.
[50] Ming-Wen Ma*, T.-Y. Yang, K.-S. Kao, T.-S. Chao, and T.-F. Lei, “Improvement on performance and reliability of TaN/HfO2 LTPS-TFTs with fluorine implantation,” International Thin Film Transistors Conference (ITC), January, Rome, Italy, pp. 352-355, Jan. 2007.
[51] Ming-Wen Ma*, K.-S. Kao, T.-S. Chao, and T.-F. Lei, “Ultra-low temperature growth of aluminum silicate dielectric formed by nitric acid,” International Workshop on Dielectric Thin Films for Future ULSI Devices Technical Program (IWDTF), Kawasaki, Japan, pp. 81-82, Nov. 2006.
[52] Ming-Wen Ma*, T.-Y. Yang, K.-S. Kao, C.-J. Su, T.-S. Chao, and T.-F. Lei, “High performance LTPS-TFTs with HfO2 gate dielectric and nitric acid pre-treatment,” International Workshop on Dielectric Thin Films for Future ULSI Devices Technical Program (IWDTF), Kawasaki, Japan, pp. 33-34, Nov. 2006.
[53] Ming-Wen Ma*, T.-S. Chao, K.-H. Kao, J.-S. Huang, and T.-F. Lei, “Impacts of high-k offset spacer on 65-nm node SOI devices,” Ninth International Conference on Modeling and Simulation of Microsystems, Boston, Massachusetts, pp. 697-700, May 2006.
[54] Ming-Wen Ma*, T.-S. Chao, K.-H. Kao, J.-S. Huang, and T.-F. Lei, “Novel FD SOI devices structure for low standby power applications,” Ninth International Conference on Modeling and Simulation of Microsystems, Boston, Massachusetts, pp. 59-62, May 2006.
[1] Yu-Wen Chou, Cheng-Yu Ma, and Chun-Jung Su, “Enhanced Ferroelectricity in 5nm Hf0.5Zr0.5O2 by Nanolaminted HfN Insertion Layers,” 2023 Symposium on Nano-Device Circuits and Technologies (SNDCT2023), AA11200014, Hsinchu, Taiwan, May 2023.
[2] Hsin-Chun Tseng, Cheng-Yu Ma, and Chun-Jung Su, “Enhanced Polarization and Reduced Leakage by in-situ Nitrided Interface on 5nm-HZO MOSCAPs,” 2023 Symposium on Nano-Device Circuits and Technologies (SNDCT2023), AA11200016, Hsinchu, Taiwan, May 2023.
[3] B.-H. Fang, S.-Y. Huang, T.-R. Wu, W.-J. Lee, N.-Y. Chen, D. Lu, K.-H. Kao, W. C.-Y. Ma and Y.-J. Lee, “Deep-Learning-Aided Design Engine Based on Physical Scalable Models and Experimental Data for Device Simulation and Inverse Design,” 2023 Symposium on Nano-Device Circuits and Technologies (SNDCT2023), AA11200023, Hsinchu, Taiwan, May 2023.
[4] Hsu-Tang Liao, Min-Kun Huang, Yeong-Her Wang, Cheng-Yu Ma, and Chun-Jung Su, “Top-gated 2D Material Transistors with NH3-plasma Treated MoS2,” 2023 Symposium on Nano-Device Circuits and Technologies (SNDCT2023), DD11200011, Hsinchu, Taiwan, May 2023.
[5] C. L. Yen, J. C. Chang, M. K. Huang, Y. H. Wang, C. J. Su, and W. C. Y. Ma, “Investigation of HfN interlayers on ferroelectricity of HfZrO2,” 2022 Symposium on Nano-Device Circuits and Technologies (SNDCT2022), EE11100016, Hsinchu, Taiwan, May 2022.
[6] J. C. Chang, C. L. Yen, M. K. Huang, Y. H. Wang, C. J. Su, and W. C. Y. Ma, “Antiferroelectricity and ferroelectricity of Si-doped HfOx thin films,” 2022 Symposium on Nano-Device Circuits and Technologies (SNDCT2022), DD11100019, Hsinchu, Taiwan, May 2022.
[7] William Cheng-Yu Ma, Chun-Jung Su, Yao-Jen Lee, Kuo-Hsing Kao, Jhe-Wei Jhu, Pin-Hua Wu, Ju-Heng Lin, Jui-Che Chang, Cheng-Lun Yen, Hsin-Chun Tseng, Hsu-Tang Liao, Yu-Wen Chou, Min-Yu Chiu, and Yan-Qing Chen, “Impacts of negative gate bias stress on ferroelectric thin-film transistor memory,” 2022 Symposium on Nano-Device Circuits and Technologies (SNDCT2022), BB11100005, Hsinchu, Taiwan, May 2022.
[8] Chia-Chuan Wu, William Cheng-Yu Ma, Yu-Xuan Wang, Mao-Chou Tai, Yu-An Chen, Pei-Jun Sun, Hong-Yi Tu, Kuan-Ju Zhou, Yu-Shan Shih, Sheng-Yao Chou, Ya-Ting Chien, Ting-Chang Chang, “Analysis of the performance and negative bias temperature instability in LTPS TFTs using low temperature process,” 2022 Symposium on Nano-Device Circuits and Technologies (SNDCT2022), AA11100038, Hsinchu, Taiwan, May 2022.
[9] William Cheng-Yu Ma, Jui-Che Chang, Pin-Hua Wu, Cheng-Lun Yen, Ju-Heng Lin, Yan-Shiuan Chang, Jhe-Wei Jhu, Ting-Hsuan Chang, and Po-Jen Chen, “Characterization of ferroelectric-TFTs for neuromorphic computing,” 2021 Symposium on Nano-Device Circuits and Technologies (SNDCT2021), BB11000013, Hsinchu, Taiwan, May 2021.
[10] William Cheng-Yu Ma, Yan-Shiuan Chang, Jhe-Wei Jhu, Ting-Hsuan Chang, Po-Jen Chen, Jui-Che Chang, Pin-Hua Wu, Cheng-Lun Yen, Ju-Heng Lin, and Hsiao-Chun Wang, “Vertically Integrated Complementary Polycrystalline-Silicon Thin-Film Transistor for Applications of Monolithic 3D-IC,” 2021 Symposium on Nano-Device Circuits and Technologies (SNDCT2021), AA11000011, Hsinchu, Taiwan, May 2021.
[11] William Cheng-Yu Ma, Cai-Jia Tsai, Shen-Ming Luo, Ming-Jhe Li, Jiun-Hung Lin, Po-Jen Chen, Yan-Shiuan Chang, Jhe-Wei Jhu and Ting-Hsuan Chang, “Length Dependence Effect of Hot Carrier Stress on Polycrystalline-Silicon Tunnel Field-Effect Transistor,” SNDT2020 The 27th Symposium on Nano Device Technology, AA00077-1, Hsinchu, Taiwan, Apr. 2020.
[12] William Cheng-Yu Ma, Che-Yu Jao, Hui-Shun Hsu, Chih-Cheng Fang, Tzu-Han Liao, Hsiao-Chun Wang, Li-Wei Yu, Jia-Yi Wang and Yan-Jia Huang, “Two-step degradation behavior in poly-Si TFET under positive gate bias stress,” SNDT2019 The 26th Symposium on Nano Device Technology, DD00049-1, Hsinchu, Taiwan, Apr. 2019.
[13] K.-H. Kao, J.-H. Chen, Ming-Wen Ma, T.-S. Chao, R.-H. Gau, Michael Y. Chiang, S.-H. Chuang, T.-F. Lei, and G.-L. Luo, “Characterization of CoTiO3 thin films formed by sol-gel spin coating with high temperature annealing,” Symposium on Nano Device Technology (SNDT), Hsinchu, Taiwan, Apr. 2007.
[14] Ming-Wen Ma*, T.-S. Chao, K.-H. Kao, J.-S. Huang, and T.-F. Lei, “Novel FD SOI devices structure for ultra low leakage applications,” Symposium on Nano Device Technology (SNDT), Hsinchu, Taiwan, pp. T5-07, Apr. 2006.
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