Restoring vs Non-Restoring Division
The restoring division algorithm is based on the principle of long division, where the divisor is subtracted from the partial remainder repeatedly until it becomes negative or zero. If the partial remainder becomes negative, the divisor is added back to restore it to a positive value, and the quotient bit is set to zero. Otherwise, the quotient bit is set to one. The restoring division algorithm requires two operations (subtraction and addition) in each iteration, and hence it is slower and more complex than the non-restoring algorithm.
The non-restoring division algorithm is based on the principle of successive approximation, where the divisor is subtracted from or added to the partial remainder depending on the sign of the previous partial remainder. If the previous partial remainder was positive, the divisor is subtracted from it, and the quotient bit is set to one. If the previous partial remainder was negative, the divisor is added to it, and the quotient bit is set to zero. The non-restoring division algorithm requires only one operation (subtraction or addition) in each iteration, and hence it is faster and simpler than the restoring algorithm. However, the non-restoring algorithm may produce a negative final remainder, which needs to be corrected by adding the divisor to it and decrementing the quotient by one.
VHDL Code for Serial Adder
A serial adder is a circuit that can perform binary addition of two numbers bit by bit using a single full adder and a register. A full adder is a combinational logic circuit that can add two bits and a carry bit and produce a sum bit and a carry out bit. A register is a sequential logic circuit that can store and shift bits. A serial adder can be implemented in VHDL using a process statement that describes the behavior of the full adder and a signal assignment statement that describes the behavior of the register. The following VHDL code shows an example of a serial adder that can add two 8-bit numbers:
library ieee; use ieee.std_logic_1164.all; entity serial_adder is port( clk : in std_logic; -- clock input rst : in std_logic; -- reset input A : in std_logic_vector(7 downto 0); -- first operand input B : in std_logic_vector(7 downto 0); -- second operand input S : out std_logic_vector(8 downto 0) -- sum output ); end serial_adder; architecture behavioral of serial_adder is signal C : std_logic_vector(8 downto 0); -- carry register signal i : integer range 0 to 8; -- loop counter begin process(clk) variable Cin : std_logic; -- carry in for full adder variable Sum : std_logic; -- sum for full adder variable Cout : std_logic; -- carry out for full adder begin if rising_edge(clk) then -- on positive edge of clock if rst = '1' then -- if reset is high C '0'); -- clear carry register i
VHDL Code for Non Restoring Division Algorithm
A non restoring division algorithm can be implemented in VHDL using a serial adder and two registers: one for the dividend and one for the partial remainder. The following VHDL code shows an example of a non restoring division algorithm that can divide two 8-bit numbers and produce an 8-bit quotient and an 8-bit remainder:
library ieee; use ieee.std_logic_1164.all; entity serial_divider is port( clk : in std_logic; -- clock input rst : in std_logic; -- reset input D : in std_logic_vector(7 downto 0); -- dividend input d : in std_logic_vector(7 downto 0); -- divisor input Q : out std_logic_vector(7 downto 0); -- quotient output R : out std_logic_vector(7 downto 0) -- remainder output ); end serial_divider; architecture behavioral of serial_divider is component serial_adder -- component declaration for serial adder port( clk : in std_logic; rst : in std_logic; A : in std_logic_vector(7 downto 0); B : in std_logic_vector(7 downto 0); S : out std_logic_vector(8 downto 0) ); end component; signal P : std_logic_vector(8 downto 0); -- partial remainder register signal Q_temp : std_logic_vector(7 downto 0); -- temporary quotient register signal i : integer range 0 to 8; -- loop counter begin adder1: serial_adder port map(clk, rst, P, not d, P); -- instantiate serial adder to perform subtraction adder2: serial_adder port map(clk, rst, P, d, P); -- instantiate serial adder to perform addition process(clk) begin if rising_edge(clk) then -- on positive edge of clock if rst = '1' then -- if reset is high P '0'); -- clear temporary quotient register i
Conclusion
In this article, we have discussed the non restoring division algorithm and how it can be implemented in VHDL using a serial adder and two registers. We have also shown the VHDL code for a serial adder and a non restoring division algorithm. The non restoring division algorithm is faster and simpler than the restoring division algorithm, but it may require a correction step at the end. The VHDL code for the non restoring division algorithm can be simulated and synthesized using any VHDL tool.
References:
[Serial-Divider-Non-Restoring-Algorithm-in-VHDL/SerialDivider ... - GitHub]
[Divide by integer in VHDL - Electrical Engineering Stack Exchange]
[tukuri/Serial-Divider-Non-Restoring-Algorithm-in-VHDL]
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