PhD Student
PhD Student
Embedded Files
AVS Lab, Dept of Computer Science and Engineering, IITG
s.nilotpola@iitg.ac.in, nilotpolasarma@gmail.com
Bio
My PhD Thesis deals with design automation, verification and debug of cryptographic hardware with power side-channel attack resistance, particularly masked hardware (CV). I am fortunate to be working under the guidance of Dr Chandan Karfa in the Department of Computer Science and Engineering at IIT Guwahati. Previously, I completed my Bachelor of Technology at IIIT Guwahati.
Tools
DSE for Masking
MaskedHLS: Domain-Specific High-Level Synthesis of Masked Cryptographic Designs
MaskedHLS is a domain-specific high-level synthesis tool designed to aid in the automated generation of secure and optimised gadget-based masked cryptographic hardware implementations from their masked C versions. At the present stage, MaskedHLS is able to generate gadget-based masked hardware with the minimum (theoretical) latency and minimum (heuresitc) number of registers (DFFs) in quadratic (in the number of circuit elements) time.
If there are two or more ways to do something, and one of those ways can result in a catastrophe, then someone will do it. - Murphy's Law
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