Hardware IP Security: Logic Locking

Logic locking is a design concealment mechanism used to protect the intellectual property (IP) integrated into modern System-on-Chip (SoC) architectures from reverse engineering, IP piracy, overproduction, and unauthorized activation. Extensive research over the past decade has investigated the applicability, feasibility, and efficacy of logic locking, including metrics to assess its effectiveness, impact at different levels of abstraction, threat model definitions, resiliency against physical attacks, tampering, and the application of machine learning. However, the security and strength of existing logic locking techniques are constantly challenged by sophisticated logical and physical attacks.

As a part of the project, we developed an enhanced logic locking algorithm protecting Hardware IPs against piracy threats. Reduced KPA to 30% at a mere mean area, power and delay overhead of 19.32%, 16.35% & 11.86%, proving efficient resilience. Additionally, I achieved a 66% reduction in processing time by designing an end-to-end automated process pipeline integrating open-source synthesis and design tools for locking benchmark circuits (ISCAS’85 & ’89), verifying, testing, and generating comprehensive reports without manual intervention.