Analog and Mixed-signal IC Design
A mixed-signal IC is an integrated circuit that combines analog and digital designs. In 3C electronic products, it is often necessary to combine mixed-signal circuit design techniques to implement certain functions or sub-functions, especially when pursuing circuit design characteristics such as high speed, low power consumption, low noise, and high resolution. Analog/mixed design often become the top priority of circuit design, this is the focus of our research. Therefore, mixed-signal ICs are often designed for specific purposes, but may also be multi-purpose standard components, and the design of mixed-signal ICs requires a very high degree of professionalism and careful use of computer-aided design tools.
High-speed Communication IC Design
With the functions of wireless and wired communication products becoming increasingly diversified and their application technologies maturing, high-speed communication integrated circuit (IC) design has emerged as one of the key technologies. The design of high-frequency, high-speed, low-noise, and low-power mixed-signal ICs has become a major technical challenge. Current research areas include delay-locked loops (DLL), phase-locked loops (PLL), RF frequency synthesizers, clock generators, clock-deskew buffers, clock and data recovery (CDR) circuits, high-speed SerDes interface design, as well as chiplet and silicon photonic chip interconnect technologies.
Advanced Circuit Design for Sensor and Energy Conversion
We are committed to the research and development of new related circuit designs that combine sensors and energy harvester, such as converting the tiny power output from micro power generation components into actual usable electrical energy, microelectromechanical sensing circuits and other related circuit research. The purpose of the research is to improve sensor sensitivity and conversion performance for sensing and energy system applications.
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類比與混合訊號積體電路設計
高速通訊積體電路設計
前瞻能源轉換電路設計
類比與混合訊號積體電路設計
混合訊號積體電路(mixed-signal IC)是結合了類比與數位設計的積體電路。在3C電子產品中,所要實行某些全部功能或子功能,常常需結合混合訊號電路設計技術,尤其當追求高速度、低功耗、低雜訊、高解析等電路設計特性時,類比電路設計往往成為電路設計的重中之重,此正為我們研究之重點。因此,混合訊號積體電路經常被設計給特定用途,但也可能是多用途的標準元件,而且混合訊號積體電路的設計需要非常高度的專業和細心的使用電腦輔助設計工具。
高速通訊積體電路設計
隨著無線與有線通訊系統之應用持續拓展,高速通訊積體電路設計已逐漸成為影響整體系統效能的關鍵技術。當前研究挑戰主要聚焦於高頻寬、低雜訊與低功耗之混合積體電路設計,以因應未來高效能運算與大數據傳輸需求。我們的研究範疇涵蓋延遲鎖定迴路(Delay-Locked Loop, DLL)、鎖相迴路(Phase-Locked Loop, PLL)、射頻頻率合成器(RF Frequency Synthesizer)、時脈產生器(Clock Generator)、時脈誤差校正電路(Clock-Deskew Buffer)、時脈與資料回復電路(Clock and Data Recovery, CDR)、高速SerDes介面設計,以及小晶片(Chiplet)互連與矽光子(Silicon Photonic)傳輸等前瞻性電路架構。透過上述研究方向的持續深化與整合,期能建構下一世代高速通訊晶片設計的核心技術基礎。
前瞻感測器和能源轉換電路設計
研發新式結合感測器和獵能器等相關電路設計,例如將微發電元件所輸出的微小電源轉換成實際可用電能、微機電感測電路等相關電路研究,研究目的為提高感測器靈敏度和轉換效能,以為感測和能源系統應用。
A 1–3 GHz Fast-Locking Frequency Synthesizer Based on a Combination of PLL and MDLL With Auto-Zero Phase-Error Compensation [IEEE Solid-State Circuits Letters, 2024]
A 17.5-to-21-GHz Current-Folding Frequency Tripler With >36-dBc Harmonic Rejection in 90-nm CMOS [IEEE Solid-State Circuits Letters, 2023]
A 17-21GHz Current-Folding Frequency Tripler With >36dBc Harmonic Rejection in 90nm CMOS [IEEE Asian Solid-State Circuit Conference (A-SSCC), 2022]
CDR CIRCUIT
A 2.7-Gb/s CDR Circuit Based on Multiplexed Recirculating Delay-Locked Loop for ±10%-SSC Clock-Embedded Display Interface [IEEE Solid-State Circuits Letters, 2022]
A 90-nm CMOS 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth [IEEE Asian Solid-State Circuit Conference (A-SSCC), 2021]
CLOCK-DESKEWING CIRCUIT
A 180-nm CMOS Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links [IEEE Transactions on on Very Large Scale Integration (VLSI) Systems, 2021]