My research interest is SW/HW co-design and implementation of computer system with field programmable gate array (FPGA) for hybrid memory/storage system. I also worked on serveral projects on top of Samsung new released KV-SSDs.
My previous work centers on design and implementation of high-speed data acquisition and broadband signal processing systems. Please see more details on the project page.
“Hardware Memory Management for Future Mobile Hybrid Memory Systems ”, F. Wen, M. Qin, P. V. Gratz, N. Reddy, Accepted in International Conference on Compilers, Architecture, and Synthesis of Embedded Systems (CASES'20, TCAD.2020.3012213).
“A Generic FPGA Accelerator for Minimum Storage Regenerating Codes”, M. Qin, J. H. Lee, R. Pitchumani, Y. S. Ki, N. Reddy, P. V. Gratz, In The 25th Asia and South Pacific Design Automation Conference (ASP-DAC'20), Jan 2020.
“SPaN: Speculative Paging for future NVM and SSD”, Viacheslav Fedorov, Jinchun Kim, Mian Qin, A. L. Narasimha Reddy and Paul Gratz. In the International Symposium on Memory Systems (MEMSYS’17), October 2017.
FPGA ACCELERATION SYSTEM FOR MSR CODES
射电天文阵列远程光纤同步系统及其方法(Remote Fiber Array radio astronomy synchronization system and method)
射电天文阵列的高可扩展性分布式DBF处理系统及方法(High-scalability distributed DBF processing system and method for radio astronomical array)
基于改进VFDF的实时宽带数字波束指向控制方法(Improved directivity control based on real-time broadband digital beam vfdf)
一种分数延迟数字滤波器的实现结构(Fractional delay digital filter implementation structure)