High Speed System Design (SERDES Circuits)

Course contents:

1. Course introduction (PDF)

2. CMOS process technology (PDF)

3. PN Junction (PDF)

4. On-chip Resistors (PDF)

5. On-chip Capacitors (PDF) 

6. On-chip Inductors (PDF)  

7. MOSFETs - Transit frequency, process variation, and mismatch (PDF)  

8. Wireline channel (PDF)  

9. Transmission-Line simulation methods (PDF)  

10. Wireline TX circuits (PDF)(Channel-S-Param)    

11. Wireline RX circuits (PDF)  

12. Continuous Time Linear Equalization (CTLE) (PDF)  

13. Decision Feedback Equalization (DFE) (PDF) 

14. Feed-Forward Equalization (FFE) (PDF)

15. Wireline circuits: case studies (PDF)

Exams and assignments:

1. Assessment-1 exam (Question) (Solution)

2. Problem solving assignment (Question) (Solution) 

3. Wireline Tx/Rx practice problems (Question) 

4. Assessment-2 exam (Question) (Solution)  

5. Final exam (Question) (Solution)   

References: 

1. "S-Parameter Design," Agilent application note (PDF). 

2. "Time Domain Reflectometry," Agilent application note (PDF).

3. "High-Speed Electrical Signaling: Overview and Limitations," Mark Horowitz, et. al., (PDF).

4. S. Palermo, “CMOS Nanoelectronics Analog and RF VLSI Circuits. Chapter 9: High-Speed Serial I/O Design for Channel-Limited and Power-Constrained Systems,” McGraw-Hill, 2011 (PDF). 

5. B. Razavi, "Design Techniques for High-Speed Wireline Transmitters," in IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 53-66, 2021 (PDF).

6. K. R. Lakshmikumar et al., "A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s PAM-4 Optical Links," in IEEE Journal of Solid-State Circuits, vol. 54, no. 11, pp. 3180-3190, Nov. 2019.

7. D. Patel, A. Sharif-Bakhtiar and T. C. Carusone, "A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes," in IEEE Journal of Solid-State Circuits, vol. 58, no. 3, pp. 771-784, March 2023.

8. B. Casper and F. O'Mahony, "Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links—A Tutorial," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 1, pp. 17-39, Jan. 2009.

9. J. F. Bulzacchelli et al., "A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology," in IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 3232-3248, Dec. 2012.

10. S. Palermo, A. Emami-Neyestanak and M. Horowitz, "A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects," in IEEE Journal of Solid-State Circuits, vol. 43, no. 5, pp. 1235-1246, May 2008.

11. V. Gurumoorthy and S. Palermo, "Supply regulation techniques for phase-locked loops," 2009 IEEE Dallas Circuits and Systems Workshop (DCAS), Richardson, TX, USA, 2009.

12. Y. -H. Song, R. Bai, K. Hu, H. -W. Yang, P. Y. Chiang and S. Palermo, "A 0.47–0.66 pJ/bit, 4.8–8 Gb/s I/O Transceiver in 65 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 48, no. 5, pp. 1276-1289, May 2013.

13. Y. -H. Song, H. -W. Yang, H. Li, P. Y. Chiang and S. Palermo, "26.5 An 8-to-16Gb/s 0.65-to-1.05pJ/b 2-tap impedance-modulated voltage-mode transmitter with fast power-state transitioning in 65nm CMOS," 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA, 2014.

14. O. Elhadidy and S. Palermo, "A 10 Gb/s 2-IIR-tap DFE receiver with 35 dB loss compensation in 65-nm CMOS," 2013 Symposium on VLSI Circuits, Kyoto, Japan, 2013.

15. H. -W. Yang, A. Roshan-Zamir, Y. -H. Song and S. Palermo, "A low-power dual-mode 20-Gb/s NRZ and 28-Gb/s PAM-4 voltage-mode transmitter," 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), Seoul, Korea (South), 2017.

16. Y. -H. Song, H. -W. Yang, H. Li, P. Y. Chiang and S. Palermo, "An 8–16 Gb/s, 0.65–1.05 pJ/b, Voltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning," in IEEE Journal of Solid-State Circuits, vol. 49, no. 11, pp. 2631-2643, Nov. 2014.

17. J. Kim, B. S. Leibowitz, J. Ren and C. J. Madden, "Simulation and Analysis of Random Decision Errors in Clocked Comparators," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 8, pp. 1844-1857, Aug. 2009.

18. J. Cao et al., "OC-192 transmitter and receiver in standard 180nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 37, no. 12, pp. 1768-1780, Dec. 2002.

19. S. Rylov et al., "10+ Gb/s 90nm CMOS serial link demo in CBGA package," Proceedings of the IEEE Custom Integrated Circuits Conference, Orlando, FL, USA, 2004.

20. J. -H. Chae, M. Kim, S. Choi and S. Kim, "A 10.4-Gb/s 1-Tap Decision Feedback Equalizer With Different Pull-Up and Pull-Down Tap Weights for Asymmetric Memory Interfaces," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 2, pp. 220-224, Feb. 2020.

21. X. Zheng et al., "A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 52, no. 11, pp. 2963-2978, Nov. 2017.