Analog Power Integrated Circuits (Linear)

Reference textbooks: 

1. "Design of Analog CMOS Integrated Circuits", Behzad Razavi (2nd edition)

2. "Analysis and Design of Analog Integrated Circuits", Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer (5th edition)

3. "Design of Power Management Integrated Circuits", Bernhard Wicht, Wiley-IEEE Press, 2024. 

4. "Power Management Techniques for Integrated Circuit Design", Ke-Horng Chen, Wiley-IEEE Press, 2016.

5. Selected papers from IEEExplore

Voltage reference circuits: 

1. X. Liao, X. Liu, Y. Wang and L. Liu, "A High-Precision Current-Mode Bandgap Reference With Low-Frequency Noise/Offset Elimination," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 11, pp. 3993-3997, Nov. 2023.

2. Z. Zhang, C. Zhan, L. Wang and M. -K. Law, "A −40°C to 125°C 0.4μA Low-Noise Bandgap Voltage Reference With 0.8mA Load Driving Capability Using Shared Feedback Resistors," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 10, pp. 4033-4037, Oct. 2022.

3. J. Wang, X. Sun and L. Cheng, "A Picowatt CMOS Voltage Reference Operating at 0.5V Power Supply With Process and Temperature Compensation for Low-Power IoT Systems," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 4, pp. 1336-1340, April 2023.

4. C. F. Lee, C. W. U, R. P. Martins and C. S. Lam, "A 0.5V 22.5ppm/°C Bandgap Voltage Reference With Leakage Current Injection for Curvature Correction," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 10, pp. 3897-3901, Oct. 2023.

5. M. Lefebvre, D. Flandre and D. Bol, "A 1.1/0.9nA Temperature-Independent 213/565 ppm/°C Self-Biased CMOS-Only Current Reference in 65nm Bulk and 22nm FDSOI," in IEEE Journal of Solid-State Circuits, vol. 58, no. 8, pp. 2239-2251, Aug. 2023.

6. D. Shetty, C. Steffan, G. Holweg, W. Bosch and J. Grosinger, "Ultra-Low-Power Sub-1 V 29 ppm/°C Voltage Reference and Shared-Resistive Current Reference," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 3, pp. 1030-1042, March 2023.

7. C. Che, K. M. Lei, R. P. Martins and P. I. Mak, "A 0.4V 8400-μm2 Voltage Reference in 65-nm CMOS Exploiting Well-Proximity Effect," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 10, pp. 3822-3826, Oct. 2023.

Low Drop Out (LDO) Voltage Regulators: 

1. N. Adorni, S. Stanzione and A. Boni, "A 10 mA LDO With 16 nA IQ and Operating From 800 mV Supply," in IEEE Journal of Solid-State Circuits, vol. 55, no. 2, pp. 404-413, Feb. 2020.

2. J. R. Huang et al., "A 10 nA Ultra-Low Quiescent Current and 60 ns Fast Transient Response Low-Dropout Regulator for Internet-of-Things," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 1, pp. 139-147, Jan. 2022. 

3. M. Luders et al., "A fully-integrated system power aware LDO for energy harvesting applications," Symposium on VLSI Circuits - Digest of Technical Papers, Kyoto, Japan, 2011, pp. 244-245. 

4. X. Mao, Y. Lu, C. Wang and R. P. Martins, "A High-Current Scalable Parallel LDO Scheme With Analog-Digital Merged Control for Small Current-Sharing Mismatch," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 10, pp. 3857-3866, Oct. 2023.

5. Y. C. Hung and D. J. Ceng, "A Sub-1 V CMOS LDO Regulator with Multiple Protections Capabilities," 2014 International Symposium on Computer, Consumer and Control, Taichung, Taiwan, 2014.

6. H. Park, W. Jung, M. Kim and H. M. Lee, "A Wide-Load-Range and High-Slew Capacitor-Less NMOS LDO With Adaptive-Gain Nested Miller Compensation and Pre-Emphasis Inverse Biasing," in IEEE Journal of Solid-State Circuits, vol. 58, no. 10, pp. 2696-2708, Oct. 2023.

7. O. Pereira-Rial, P. Lopez, J. M. Carrillo, V. M. Brea and D. Cabello, "An 11 mA Capacitor-Less LDO With 3.08 nA Quiescent Current and SSF-Based Adaptive Biasing," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 3, pp. 844-848, March 2022.

8. A. Nakhlestani, S. V. Kaveri, M. Radfar and A. Desai, "Low-Power Area-Efficient LDO With Loop-Gain and Bandwidth Enhancement Using Non-Dominant Pole Movement Technique for IoT Applications," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 2, pp. 692-696, Feb. 2021. 

9. C. C. Liu and C. Chen, "An ultra-low power voltage regulator for RFID application," IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, OH, USA, 2013, pp. 780-783

10. J. S. Kim, K. Javed and J. Roh, "Design of a Low-Power and Area-Efficient LDO Regulator Using a Negative-R-Assisted Technique," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 10, pp. 3892-3896, Oct. 2023.

11. J. S. Kim, K. Javed, K. H. Min and J. Roh, "A 13.5-nA Quiescent Current LDO With Adaptive Ultra-Low-Power Mode for Low-Power IoT Applications," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 9, pp. 3278-3282, Sept. 2023.

12. K. C. Woo and B. D. Yang, "A 0.35 V, 90nA Quiescent Current Output-Capacitor-Less NMOS Low-Dropout Regulator Using a Coarse-Fine Charge-Pump Circuit," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 12, pp. 3118-3122, Dec. 2020.