I am an Assistant Professor in the Department of Information Technology and Electrical Engineering at ETH Zurich, where I lead the Digital Systems and Design Automation Group.
Before joining ETHZ, I completed my PhD in Computer and Communication Sciences at EPFL, Switzerland, advised by Prof. Paolo Ienne. My PhD research was generously supported by the Google PhD Fellowship for Systems and Networking and the EPFL EDIC Doctoral Fellowship. Prior to my PhD, I received a MSc and BSc in Electrical Engineering and Information Technology from the University of Zagreb, Croatia.
Contact: ljosipovic at ethz.ch
My current research focuses on methods to enable generating good-quality hardware designs from high-level programming languages. My goal is to bridge the gap between software and hardware by developing language abstractions, compiler flows, and hardware devices that enable software developers from different domains to accelerate emerging compute-intensive applications. My research interests include compilers, digital hardware design, and computer architecture.
I developed Dynamatic, an open-source HLS compiler that produces dynamically scheduled, dataflow circuits out of C/C++ code. The resulting circuits achieve good performance out-of-the-box and realize behaviors that are beyond the capabilities of standard HLS tools. In addition to a complete HLS methodology, Dynamatic incorporates mathematical models to optimize the performance and area of the resulting circuits, as well as techniques to achieve characteristics that standard HLS cannot support, such as out-of-order memory accesses and speculative execution. These contributions redefine the HLS paradigm by introducing characteristics of modern superscalar processors to hardware designs; they are key for specialized computing to be successful in new contexts and broader application domains.
Awards and Honors
Please visit my group's website for a full and up-to-date publication list.
Lana Josipović, Axel Marmet, Andrea Guerrieri, and Paolo Ienne. Resource sharing in dataflow circuits. In Proceedings of the 30th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'22), pages 1–9, New York, NY, May 2022. Best Paper Award Nominee.
Lana Josipović, Andrea Guerrieri, and Paolo Ienne. From C/C++ code to high-performance dataflow circuits. IEEE Transactions on Computer-Aided Design (TCAD). August 2021.
Lana Josipović, Andrea Guerrieri, and Paolo Ienne. Synthesizing general-purpose code into dynamically scheduled circuits. IEEE Circuits and Systems Magazine (CASM), 21(2):97–118, May 2021.
Lana Josipović, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, and Jordi Cortadella. Buffer placement and sizing for high-performance dataflow circuits. In Proceedings of the 28th ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays (FPGA’20), pages 186–96, Seaside, Calif., February 2020. Best Paper Award.
Lana Josipović, Atri Bhattacharyya, Andrea Guerrieri, and Paolo Ienne. Shrink it or shed it! Minimize the use of LSQs in dataflow designs. In Proceedings of the IEEE Intl. Conference on Field Programmable Technology (FPT’19), pages 197–205, Tianjin, China, December 2019.
Lana Josipović, Radhika Ghosal, and Paolo Ienne. Dynamically scheduled high-level synthesis. In Proceedings of the 26th ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays (FPGA’18), pages 127–36, Monterey, Calif., February 2018. Best Paper Award Nominee.