Lana Josipović

I am an Assistant Professor in the Department of Information Technology and Electrical Engineering at ETH Zurich, where I lead the Digital Systems and Design Automation Group.

Before joining ETHZ, I completed my PhD in Computer and Communication Sciences at EPFL, Switzerland, advised by Prof. Paolo Ienne. My PhD research was generously supported by the Google PhD Fellowship for Systems and Networking and the EPFL EDIC Doctoral Fellowship. Prior to my PhD, I received a MSc and BSc in Electrical Engineering and Information Technology from the University of Zagreb, Croatia.

Contact: ljosipovic at ethz.ch

For info on open PhD positions, MSc and BSc projects, and internships, please visit my group's website.

Research

My current research focuses on methods to enable generating good-quality hardware designs from high-level programming languages. My goal is to bridge the gap between software and hardware by developing language abstractions, compiler flows, and hardware devices that enable software developers from different domains to accelerate emerging compute-intensive applications. My research interests include compilers, digital hardware design, and computer architecture.

I developed Dynamatic, an open-source HLS compiler that produces dynamically scheduled, dataflow circuits out of C/C++ code. The resulting circuits achieve good performance out-of-the-box and realize behaviors that are beyond the capabilities of standard HLS tools. In addition to a complete HLS methodology, Dynamatic incorporates mathematical models to optimize the performance and area of the resulting circuits, as well as techniques to achieve characteristics that standard HLS cannot support, such as out-of-order memory accesses and speculative execution. These contributions redefine the HLS paradigm by introducing characteristics of modern superscalar processors to hardware designs; they are key for specialized computing to be successful in new contexts and broader application domains.

Awards and Honors

Distinguished Artifact Award at ISCA 2025.
Distinguished Reviewer Award at ASPLOS 2025
1st place at AMD/UCLA ML Contest for Chip Design with HLS (Prediction Task), PhD student Emmet Murphy
Best Reviewer Award at ICCAD 2024
Nature's 2024 Inspiring Women in Science Shortlist
Best Paper Award at FPL 2024
Best Paper Award Nominee at ICCAD 2023
Two Best Paper Nominations at FPL 2022
Best Paper Award Nominee at FCCM 2022
Electronic Design and Automation Association (EDAA) Outstanding Dissertations Award (2022)
EPFL Doctorate Award (2022)
Fritz Kutter Award for best Swiss industry-related PhD thesis in Computer Science, awarded by ETH Zurich (2021)
EPFL doctoral thesis distinction for high-quality PhD thesis (2021)
Patrick Denantes Memorial Prize for an outstanding doctoral thesis, awarded by the IC School, EPFL (2021)
Best Paper Award at FPGA 2020
Google PhD Fellowship for Systems and Networking (2018)
Best Paper Award Nominee at FPGA 2018
Best Paper Award Nominee at CASES 2017
EPFL EDIC Doctoral Fellowship (2015)
Google Anita Borg (Women Techmakers) Scholarship (2015)
Dean’s awards, Univ. of Zagreb, for outstanding achievements in the BSc (‘11, ‘12, ‘13) and MSc (‘15) studies
Scholarship for gifted students, Univ. of Zagreb, for the top 1% most successful students (’14, ’15)

Service

Associate Editor
- - IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems (TCAD), from 2024.
  - ACM Transactions on Design Automation of Electronic Systems (TODAES), from 2024.
  - ACM Transactions on Reconfigurable Technology and Systems (TRETS), from 2022.
Organizing Committee Member
- - Track Co-Chair (RTL/Logic Level and High-Level Synthesis), Design Automation Conference (DAC) 2025.
  - Finance Chair, International Workshop on Logic Synthesis (IWLS) 2025.
  - Program Vice-Chair, International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2025.
  - General Chair, International Workshop on Logic Synthesis (IWLS) 2024.
  - Program Chair, International Conference on Field-Programmable Logic and Applications (FPL) 2024.
  - Program Vice-Chair, International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2024.
  - Program Chair, International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), 2024.
  - Topic Chair (System-Level Design Methodologies and HLS), Design, Automation and Test in Europe Conference (DATE) 2024.
  - Track Chair (Electronic Design Automation), International Conference on Computer Design (ICCD) 2023.
  - Program Chair, International Workshop on Logic Synthesis (IWLS) 2023.
  - Program Chair, Reconfigurable Architectures Workshop (RAW) 2023.
  - Sponsorship Chair, International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2023.
  - Topic Co-Chair (System-Level Design Methodologies and HLS), Design, Automation and Test in Europe Conference (DATE) 2023.
  - Program Chair, Reconfigurable Architectures Workshop (RAW) 2022.
  - Workshop & Tutorial Chair, Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2022.
  - Sponsorship Chair, International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2022.
Program Committee Member
- - International Symposium on Microarchitecture (MICRO) 2026.
  - International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2026.
  - International Conference on Computer-Aided Design (ICCAD) 2025.
  - International Conference on Field-Programmable Logic and Applications (FPL) 2025.
  - Design Automation Conference (DAC) 2025.
  - International Symposium on Field-Programmable Gate Arrays (FPGA) 2025.
  - International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2025.
  - International Symposium on High-Performance Computer Architecture (HPCA) 2025.
  - International Conference on Computer-Aided Design (ICCAD) 2024.
  - International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2024.
  - International Symposium on Computer Architecture (ISCA) 2024.
  - International Symposium on Field-Programmable Gate Arrays (FPGA) 2024.
  - Design, Automation and Test in Europe Conference (DATE) 2024.
  - International Conference on Field Programmable Technology (FPT) 2023.
  - International Conference on Computer-Aided Design (ICCAD) 2023.
  - International Conference on Computer Design (ICCD) 2023.
  - 26th Euromicro Conference Series on Digital System Design (DSD) 2023.
  - International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) 2023.
  - International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2023.
  - International Workshop on Logic Synthesis (IWLS) 2023.
  - Reconfigurable Architectures Workshop (RAW) 2023.
  - International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2023.
  - International Symposium on Field-Programmable Gate Arrays (FPGA) 2023.
  - Design, Automation and Test in Europe Conference (DATE) 2023.
  - International Conference on Field Programmable Technology (FPT) 2022.
  - International Conference on Computer Design (ICCD) 2022.
  - Forum on Specification & Design Languages (FDL) 2022.
  - Reconfigurable Architectures Workshop (RAW) 2022.
  - International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2022.
  - Design, Automation and Test in Europe Conference (DATE) 2022.
  - International Conference on VLSI Design (VLSID) 2022.
  - Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE) 2021, co-located with ASPLOS'21.

Selected Publications

Please visit my group's website for a full and up-to-date publication list.

Emmet Murphy and Lana Josipović. Balor: HLS Source Code Evaluator Based on Custom Graphs and Hierarchical GNNs. In Proceedings of the Intl. Conference on Computer-Aided Design, pages 1–9, Newark, NJ, October 2024. 1st place at ML Contest for Chip Design with HLS (Prediction task).
Hanyu Wang, Carmine Rizzi, and Lana Josipović. MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization. In Proceedings of the Intl. Conference on Computer-Aided Design (ICCAD’23). To appear. Best Paper Award Nominee.
Jiahui Xu, Emmet Murphy, Jordi Cortadella, and Lana Josipović. Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking. In Proceedings of the 31st ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays (FPGA’23), pages 27–37, Monterey, CA, February 2023.
Lana Josipović, Axel Marmet, Andrea Guerrieri, and Paolo Ienne. Resource sharing in dataflow circuits. In Proceedings of the 30th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'22), pages 1–9, New York, NY, May 2022. Best Paper Award Nominee.
Lana Josipović, Andrea Guerrieri, and Paolo Ienne. From C/C++ code to high-performance dataflow circuits. IEEE Transactions on Computer-Aided Design (TCAD). August 2021.
Lana Josipović, Andrea Guerrieri, and Paolo Ienne. Synthesizing general-purpose code into dynamically scheduled circuits. IEEE Circuits and Systems Magazine (CASM), 21(2):97–118, May 2021.
Lana Josipović, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, and Jordi Cortadella. Buffer placement and sizing for high-performance dataflow circuits. In Proceedings of the 28th ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays (FPGA’20), pages 186–96, Seaside, Calif., February 2020. Best Paper Award.
Lana Josipović, Andrea Guerrieri, and Paolo Ienne. Dynamatic: From C/C++ to dynamically scheduled circuits. In Proceedings of the 28th ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays (FPGA’20), pages 1–10, Seaside, Calif., February 2020.
Lana Josipović, Radhika Ghosal, and Paolo Ienne. Dynamically scheduled high-level synthesis. In Proceedings of the 26th ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays (FPGA’18), pages 127–36, Monterey, Calif., February 2018. Best Paper Award Nominee.
Lana Josipović, Philip Brisk, and Paolo Ienne. An out-of-order load-store queue for spatial computing. In Proceedings of the Intl. Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES’17), Seoul, Korea, October 2017. See ACM TECS paper below. Best Paper Award Nominee.
Lana Josipović, Philip Brisk, and Paolo Ienne. An out-of-order load-store queue for spatial computing. ACM Transactions on Embedded Computing Systems (TECS’17), 16(5s):125:1–125:19, September 2017.

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