University of California Berkeley, USA
Early Career Award Winner 2019 IEEE Newsletter article
"Industry Standard FDSOI Compact Model BSIM-IMG for IC Design", Link
Description: This book helps readers to develop an understanding of a FDSOI device physics and its modeling. It explains questions like how FDSOI enables further scaling and why it offers unique possibilities in circuits.
Most of my Ph.D. work on FDSOI transistor characterization and modeling has been included in following chapters:
- Chapter 8: High-Frequency and Noise Models in BSIM-IMG (IEEE MTT 2016, IEEE MTT 2017, IEEE JEDS 2016)
- Chapter 7: Testing BSIM-IMG Model Quality (IEEE INDICON 2014, IEEE EDSSC 2016)
- Chapter 6:Parameter Extraction With BSIM-IMG Compact Model (Developed methodology as model Co developer, see BSIM-IMG Manual-Link)
- Chapter 4: Leakage Current and Thermal Effects (IEEE TED 2017, Microelectronics Journal 2016)
- Chapter 3: Channel Current Model With Real Device Effects in BSIM-IMG (SSE 2015)
- Chapter 2: Core Model for Independent Multigate MOSFETs (IEEE INDICON 2014)
- Novel device architectures for sub-10nm regime (Nanowire/Nanosheets)
- Characterization and analytical compact modeling of low power devices (FDSOT, FinFETs etc.).
- Energy efficient devices (NCFETs)
Awards and Recognition:
2019: Received IEEE EDS Early Career Award (First Indian Women Recipient)
2019: Latest work on negative capacitance FET transistors (IEEE EDL vol. 40, no. 3, March 2019) featured on the cover page of IEEE Electron Device Letters.
2018: Appeared in IEEE Electron Device Society golden list of reviewers.
2018: Invited Speaker in Workshop on Compact Modeling, Anaheim, USA.
2017: Research work is highlighted by IEEE Women in Engineering Society.
2015: Travel grant from Department of Science and Technology (DST) for IEEE DRC conference.
2014: Best paper award in IEEE India conference (INDICON), Pune, India, Dec. 2014.
2013: Best paper award in IEEE PrimeAsia Conference, Visakhapatnam, Dec. 2013.
2011: Best teaching skill award in Wipro’s Mission 10X program at Kanpur Institute of Technology, Kanpur, India.
2011: Gold medal for academic excellence in M.tech Microelectronics at Panjab University, Chandigarh, India.
2010: Best Student Award in IEEE ICAER'10 conference, U.I.E.T Chandigarh, India.
Reviewer of reputed journals like IEEE Transactions on Electron Devices, IEEE Electron Device Letters and Solid-State Electronics etc.
Modeling of Substrate Depletion, Self-heating, Noise and High Frequency Effects in Fully Depleted SOI MOSFETs
Abstract: Fully Depleted Silicon on Insulator (FDSOI) is a planar process technology that has replaced bulk Si transistor in advanced CMOS process nodes. It has several benefits such as reduced short channel effects, immunity against random dopant fluctuation and threshold voltage tuning facility via back-bias. FDSOI has many inherent challenges due to its structure and some of key issues are self-heating, substrate depletion, higher flicker and substrate coupled thermal noise. As industry has opted FDSOI technology below 28 nm technology node, it is very important to come up with a computationally efficient compact model which can predict all above effects to exploit the benefits of FDSOI transistors. In this thesis, we have investigated the physics behind these effects and modeled them. All the developed models are validated with the state-of-the- art experimental data.