Cyber-Physical Computing Lab.

Superconductor Computing

• Koki Ishida, Il-Kwon Byun, Ikki Nagaoka, Kosuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto,  Takatsugu Ono, Jangwoo Kim, and Koji Inoue, "SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices," International Symposium on Microarchtecture  (MICRO), pp.58-72, Oct. 2020. (acceptance rate: 82/446=18.4%) (IEEE Micro Top Picks from 2020, "Superconductor Computing for Neural Networks")

• Koki Ishida, Masamitsu Tanaka, Ikki Nagaoka, Takatsugu Ono, Satoshi Kawakami, Teruo Tanimoto, Akira Fujimaki, and Koji Inoue, “32 GHz 6.5 mW Gate-Level-Pipelined 4-bit Processor using Superconductor Single-Flux-Quantum Logic,” 2020 Symposia on VLSI Technology and Circuit (VLSI symposium), pp.1-2, June 2020.

• Ikki Nagaoka, Masamitsu Tanaka, Koji Inoue, and Akira Fujimaki, “A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic,” 2019 IEEE International Solid-State Circuits Conference (ISSCC), pp.460-462, Feb. 2019.

Quantum Computing

• Dongmoon Min, Junpyo Kim, Junhyuk Choi, Ilkwon Byun, Masamitsu Tanaka, Koji Inoue, and Jangwoo Kim, “QIsim: Architecting 10+K Qubit QC Interfaces Toward Quantum Supremacy,” ACM/IEEE International Symposium on Computer Architecture (ISCA), pp.1-16, June 2023.  (acceptance rate: 79/372=21.2%)

• Yasunari Suzuki, Takanori Sugiyama, Tomochika Arai, Wang Liao, Koji Inoue, and Teruo Tanimoto, “Q3DE: A fault-tolerant quantum computer architecture for multi-bit burst errors by cosmic rays,” the 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), pp.1110-1125, Oct. 2022.  (acceptance rate: 83/366=22.7%)

• Ilkwon Byun, Junpyo Kim, Dongmoon Min, Ikki Nagaoka, Kosuke Fukumitsu, Iori Ishikawa, Teruo Tanimoto, Masamitsu Tanaka, Koji Inoue, and Jangwoo Kim, "XQsim: Modeling Cross-Technology Control Processors for 10+K Qubit Quantum Computers," ACM/IEEE International Symposium on Computer Architecture (ISCA), pp.366-382, June 2022.  (acceptance rate: 67/400=16.8%)

Nanophotonic Computing

• Kenichi Kitayama, Masaya Notomi, Makoto Naruse, Koji Inoue, Satoshi Kawakami, and Atsushi Uchida, “Novel frontier of photonics for data processing - Photonic accelerator,” APL Photonics, Vol.4, No.9, pp.090901-1-090901-24, Sep. 2019. 

General Purpose Computing

• Hiroshi Sasaki, Satoshi Imamura, and Koji Inoue, "Coordinated Power-Performance Optimization in Manycores," In Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (PACT), pp.51-62, Sep. 2013. (acceptance rate: 36/208=17.3%)

• Hiroshi Sasaki, Teruo Tanimoto, Koji Inoue, and Hiroshi Nakamura, "Scalability-Based Manycore Partitioning," International Conference on Parallel Architectures and Compilation Techniques (PACT), pp.107-116, Sep. 2012. (acceptance rate: 39/207=18.8%)

• Koji Inoue, Tohru Ishihara, and Kazuaki Murakami, "Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption,'' Proc. of 1999 International Symposium on Low Power Electronics and Design (ISLPED), pp.273-275, Aug. 1999. (cited by 414 papers: google scholar  2020)

• Koji Inoue, Koji Kai, and Kazuaki Murakami, "Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs,'' Proc. of The Fifth International Symposium on High-Performance Computer Architecture (HPCA), pp.218-222, Jan. 1999. (My 1st international talk!)

High Performance Computing

• Yuichi Inadomi, Tapasya Patki, Koji Inoue, Mutsumi Aoyagi, Barry Rountree, Martin Schulz, David Lowenthal, Yasutaka Wada, Keiichiro Fukazawa, Masatsugu Ueda, Masaaki Kondo, and Ikuo Miyoshi, “Analyzing and Mitigating the Impact of Manufacturing Variability in Power-Constrained Supercomputing,” ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis (SC), pp.1-12, Nov. 2015.  (acceptance rate: 79/358=22.1%)

• R. Susukita, H. Ando, M. Aoyagi, H. Honda, Y. Inadomi, K. Inoue, S. Ishizuki, Y. Kimura, H. Komatsu, M. Kurokawa, K. Murakami, H. Shibamura, S. Yamamura, Y. Yu, "Performance Prediction of Large-scale Parallel System and Application using Macro-level Simulation," International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Nov. 2008. (acceptance rate: 59/277=21.3%)

Steering Committee Member

• MICRO Dec. 2018 - June 2020

General Chair

• MICRO 2018 (IEEE Computer Society,  ACM SIGARCH Computer Architecture Today) 

• MPSoC 2011

• ISLPED 2011 (Vice GC) 

TPC Member (E: External)

• IEEE Micro Top Picks 2018, 2022, 2023, 2024

• ISCA 2016, 2017, 2018, 2019, 2020(E), 2021, 2022, 2023, 2024

• MICRO 2014(E), 2016, 2020, 2021, 2022, 2023

• ASPLOS 2023(E)

• HPCA 2017(E), 2018, 2020, 2021, 2022, 2023, 2024

• SC 2011, 2016, 2022

Committee Member

• ACM SIGMICRO Executive Committee Member, July 2023 - June 2026.

Editor

• IEEE Computer Architecture Letters (CAL) editorial board Aug. 2020 - 

国内

• 情報処理学会システムアーキテクチャ研究会 主査 2018年4月〜2022年3月

2017年 Design Contest Award Honorable Mention, The 23rd International Symposium on Low Power Electronics and Design

2008年 科学技術分野の文部科学大臣表彰 若手科学者賞 

2000年 情報処理学会創立40周年記念論文賞