Profile
Takuto Kanamori
金森拓斗
Kise Laboratory, Department of Computer Science, Tokyo Institute of Technology (Tokyo Tech)
E-mail: kanamori (at) arch.cs.titech.ac.jp
Academic background
Bachelor of Engineering in Department of Computer Science, School of Engineering, Tokyo Institute of Technology, Japan, March 2020
Master of Engineering in Computer science, Department of Computer Science, School of Computing, Tokyo Institute of Technology, Japan, March 2022
Research area
・Computer Architecture
・FPGA
Journal
Takuto KANAMORI, Takashi ODAN, Kazuki HIROHATA, Kenji KISE, RVCar: An FPGA-Based Simple and Open-Source Mini Motor Car System with a RISC-V Soft Processor, IEICE Transactions on Information and Systems, 2022, Volume E105, Issue 12, Pages 1999-2007, Released 2022/12/01, Online ISSN 1745-1361, Print ISSN 0916-8532, https://doi.org/10.1587/transinf.2022PAP0004,
Hiromu MIYAZAKI, Takuto KANAMORI, Md Ashraful ISLAM, Kenji KISE, RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining, IEICE Transactions on Information and Systems, 2020, Volume E103.D, Issue 12, Pages 2494-2503, Released December 01, 2020, Online ISSN 1745-1361, Print ISSN 0916-8532.
International Conference
T. Kanamori and K. Kise, "RVCoreP-32IC: An optimized RISC- V soft processor supporting the compressed instructions," 2021 IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2021, pp. 38-45, doi: 10.1109/MCSoC51149.2021.00014.
T. Odan, T. Kanamori and K. Kise, "A function-rich FPGA system of camera image processing for video meeting," 2021 IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2021, pp. 31-37, doi: 10.1109/MCSoC51149.2021.00013.
F. Hamanaka, T. Kanamori and K. Kise, "A Low Cost and Portable Mini Motor Car System with a BNN Accelerator on FPGA," 2021 IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2021, pp. 84-91, doi: 10.1109/MCSoC51149.2021.00020.
Technical Committee
Hiromu Miyazaki, Takuto Kanamori, Md Ashraful Islam, and Kenji Kise, "Design and implementation of a RISC-V soft processor adopting five-stage pipelining", IEICE Technical Report, Vol. 119, No. 373, VLD2019-73, CPSY2019-71, RECONF2019-63, pp. 123-128, January 2020.
Takuto Kanamori, Hiromu Miyazaki, and Kenji Kise, "Design and implementation of a RISC-V soft processor targeting on FPGA-based embedded systems", IPSJ SIG Technical Report , EMB-2020-54, June 2020.
Preprint
Hiromu Miyazaki, Takuto Kanamori, Md Ashraful Islam, Kenji Kise: RVCoreP : An optimized RISC-V soft processor of five-stage pipelining, arXiv:2002.03568 [cs.AR] (2020-02-10).
Takuto Kanamori, Hiromu Miyazaki, Kenji Kise: RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions, arXiv:2011.11246 [cs.AR] (2020-11-23).
Thesis
Takuto Kanamori "圧縮命令に対応したRISC-Vソフトプロセッサの設計と実装", Bachelor thesis, Department of Computer Science, School of Engineering, Tokyo Institute of Technology, March 2020.
Takuto Kanamori "RISC-Vソフトプロセッサを用いたモーターカーシステム", Master thesis, Department of Computer Science, School of Engineering, Tokyo Institute of Technology, March 2022.
GitHub