Joong Hyun An

Introduction

Joonghyun An received the M.S. degree in School of Electronics Engineering from Kyungpook National University, Daegu, Korea, in 2017. His research interests include ultra-low power VLSI chip design for IoT-driven applications and implementing machine learning. He has a lot of experience in the design of System on Chip (SoC) for embedded systems such as MCUs, and is currently developing ARM-based NAND flash controllers with Custom-Designed VLSI circuits at SK Hynix Semiconductor. He published several journal/conference papers related robust processor architecture protecting abnormal clock failure.

Publications

  • Automatic on-chip backup clock changer for protecting abnormal MCU operations in unsafe clock frequency

J An, MG Seok, D Park

IEICE Electronics Express, 13.20160808

  • Automatic on-chip glitch-free backup clock changing method for mcu clock failure protection in unsafe i/o pin noisy environment

J An, J Youn, J Cho, D Park

Journal of The Institute of Electronics and Information Engineers 52 (12 …

  • On-chip glitch-free backup clock changer with noise canceller and edge detector for safety MCU clock system

J An, J Cho, D Park

2015 IEEE 4th Global Conference on Consumer Electronics (GCCE), 487-488

  • Safe Adaptive Headlight Controller with Symmetric Angle Sensor Compensator Using Steering-swivel Angle Lookup Table

J Youn, J An, MD Yin, J Cho, D Park

Transactions of the Korean Society of Automotive Engineers 24 (1), 112-121

  • Acoustic event detection-based individualized things-human interaction using Matlab-microcontroller interoperation

SS Kim, J An, J Cho, D Park

2016 IEEE 5th Global Conference on Consumer Electronics, 1-2


Google Scholar

Projects

  • Embedded Flash+EEPROM Combi General Micocontroller with Common Function

  • Embedded Flash+EEPROM Combi Micocontroller with ROM Encryption

  • HDMI-CEC Compliant Microcontroller Design

  • Low Power 3D Glasses Sync Processor for 3D TV

  • Dedicated Microcontroller for LED BLU control

  • Microcontroller with Driver & DC-DC One chip Solution

  • Flash Control device with UFS 2.0 host protocol

  • Flash Control device with eMMC 5.1 host protocol

  • Flash Control device with UFS 3.0/2.1 Combi host protocol

  • NAND PHY IP design for high speed NAND Flash access

Techniques

  • Language

    • Verilog HDL, C programming, C-shell, Tcl, Perl

  • Tool

    • NCVerilog, VCS, Simvision, Verdi, Design Compiler, Prime Time, Formality, Vivado, Altera

Contacts