Jinkwon Kim

Ph.D. Student, School of Computing, KAIST.

My primary interest lies in cross-layer optimizations for efficient compression-based systems. I have optimized several different compression-based systems through cross-layer optimizations. (e.g., sparse tensor accelerator [MICRO'23], main memory [HPCA’22], DNN [DATE’22, TC'23], CPU ISA [TC’21], and SSD [TC’22]). The PDF version of CV is available at the link.

Email: coco@kaist.ac.kr
Phone: +82-10-2754-9153

Education

Integrated M.S. and Ph.D. in School of Computing, KAIST, Mar. 2017 - Feb. 2024 (Expect)
- Advisor: Soontae Kim
Bachelor, Double Majors in Industrial Engineering and Computer Science and Engineering, Mar. 2012 - Aug. 2016

Publications

[MICRO, Top-tier] Jinkwon Kim, Myeongjae Jang, Haejin Nam, and Soontae Kim, “HARP: Hardware-Based Pseudo-Tiling for Sparse Matrix Multiplication Accelerator”, accepted in IEEE/ACM International Symposium on Microarchitecture (MICRO), 2023.
[TC, SCI] Myeongjae Jang, Jinkwon Kim, Haejin Nam, and Soontae Kim, “Zero and Narrow-width Value-aware Compression for Quantized Convolutional Neural Networks”, accepted in IEEE Transactions on Computers (TC)
[TC, SCI] Mincheol Kang, Wonyoung Lee, Jinkwon Kim, and Soontae Kim, “PR-SSD: Maximizing Partial Read Potential by Exploiting Compression and Channel-Level Parallelism”, IEEE Transactions on Computers (TC), Vol.72, No.3, pp.772-785, May 2022.
[DATE, Major] Myeongjae Jang, Jinkwon Kim, Jesung Kim, and Soontae Kim, “ENCORE Compression: Exploiting Narrow-width Values for Quantized Deep Neural Networks”, Design, Automation, and Test in Europe (DATE), Antwerp, Belgium, Mar 2022.
[HPCA, Top-tier] Jinkwon Kim, Mincheol Kang, Jeongkyu Hong, and Soontae Kim, “Exploiting Inter-block Entropy to Enhance the Compressibility of Blocks with Diverse Data”, IEEE International Symposium on High-Performance Computer Architecture (HPCA), Seoul, South Korea, Apr 2022. [Conference Slide (PPT/Short)] [Dissertation Proposal Slide (PPT/Long)]
[TC, SCI] Jinkwon Kim, Seokin Hong, Jeongkyu Hong, and Soontae Kim, “CID: Co-Architecting Instruction Cache and Decompression System for Embedded Systems”, IEEE Transactions on Computers (TC), Vol.70, No.7, pp.1132-1145, Jul 2021.

Research Experiences

Hardware-based Pseudo-Tiling for Sparse Matrix Multiplication Accelerator
- - Redefine the boundary between hardware and software for tiling in sparse matrix multiplication.
  - Identify the limitations of the software-baed tiling: manual execution, generation of several compression formats for each tile, and ineffectual accesses.
  - Introduce a hardware-based pseudo-tiling, which performs the tiling process in hardware instead of software to overcome the aforementioned limitations of the software-based tiling.
  - The hardware-based pseudo-tiling allows logical tiling of the original compressed matrix without generating a compression format for each tile and skips ineffectual accesses for input matrices.
  - Accepted in MICRO 2023.

Maximizing Partial Read Potential by Exploiting Compression and Channel-Level Parallelism
- Propose a new compression algorithm for applying partial read operations in SSD, and a split module that can use partial read operation for uncompressed requests via channel-level parallelism in SSD.
- Published in TC 2022

Exploiting Narrow-Width Values to Reduce Data Traffic in Quantized Deep Neural Networks
- Propose a new compression algorithm based on the narrow-width value property in modern quantized DNN to reduce data traffic.
- Published in DATE 2022 and accepted in TC 2023

Exploiting Inter-Block Entropy to Improve the Compressibility of Blocks with Diverse Data
- Analyze software-layer characteristics to overcome the limitations of previous intra- and inter-block compression techniques and identify two types of low-entropy among blocks. Based on these two low-entropy types, we introduce an entropy-based inter-block pattern compression technique.
- Propose hardware-based and profiling-based pattern selection methods to efficiently manage inter-block patterns.
- Propose a hybrid approach that leverages both intra- and inter-block compression techniques.
- Published in HPCA 2022

Co-Design Compression-Support Architecture and Code Compression for Low-Power and Low-Area
- Discover that certain bits within the 32-bit instruction encoding in RISC ISAs have high entropy due to several characteristics of high-level languages, such as reusability and the calling convention.
- Based on these observations, we re-organize the hardware components of the code compression-support architecture and design the instruction cache architecture to efficiently support the proposed code compression technique.
- Published in TC 2021

Skills

Programmings: C++, C, Python, Verilog, Chisel
Architecture Simulators and Tools: Gem5, Zsim, SST, Pin, DRAMSim2, Ramulator, DRAMPower, McPAT, CACTI, Synopsys Design Compiler
System Software: Linux, Warewulf HPC Cluster, QEMU

Awards & Scholarships

National Scholarship, KAIST 2017 - present
Summa Cum Laude, Hanyang University 2016

Teaching Experiences

Teaching Assistant for Digital System and Lab, KAIST Spring 2020
Teaching Assistant for Computer Architecture, KAIST Spring 2019
Teaching Assistant for Computer Organization, KAIST Fall 2018
Teaching Assistant for Computer Organization, KAIST Spring 2018
Teaching Assistant for Computer Organization, KAIST Fall 2018