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Jinchun Kim

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cienlux@gmail.com

About me

I work at Apple as a GPU engineer. I completed my Ph.D. at Texas A&M University where I did a lot of fun stuffs with my advisor Dr. Paul V. Gratz. Most of my works are focused on future memory system design and prediction mechanisms but I like everything related to building a faster and more energy-efficient microprocessor.

I am also a main developer of ChampSim and organized the simulation infrastructure for the 2nd Cache Replacement Championship (CRC-2). If you have any questions about ChampSim or CRC-2, please post your questions on the public mailing list. You can sign up to the mailing list by sending an empty mail to champsim+subscribe@googlegroups.com.

Note that this is a personal webpage to keep track of my public records. Nothing in this webpage represents my current or previous employers.

Publication

  • [MEMSYS '17] "Speculative Paging for Future NVM and SSD", Viacheslav Fedorov, Jinchun Kim, Mian Qin, A. L. Narasimha Reddy, Paul Gratz. The International Symposium on Memory Systems (MEMSYS), October 2017. (PDF)
  • [ASPLOS '17] "Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy", Jinchun Kim, Elvira Teran, Paul. V. Gratz, Daniel A. Jiménez, Seth H. Pugsley, and Chris Wilkerson. The 22nd ACM International Conference on Architectural Support for Programming Language and Operating Systems (ASPLOS), April 2017. (PDF)
  • [MICRO '16] "Path Confidence based Lookahead Prefetching", Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy, Chris Wilkerson, and Zeshan Chishti. The 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2016. Nominated for best paper (PDF)
  • [MEMSYS '15] "Dynamic Memory Pressure Aware Ballooning", Jinchun Kim, Viacheslav Fedorov, Paul V. Gratz, and A. L. Narasimha Reddy. The International Symposium on Memory Systems (MEMSYS), October 2015. (PDF)
  • [DPC-2] "Lookahead Prefetching with Signature Path", Jinchun Kim, Paul V. Gratz, A. L. Narasimha Reddy. The 2nd Data Prefetching Championship (DPC-2), June 2015. (PDF, Code)
  • [DAC '15] "A Bandwidth Efficient On-Chip Interconnects Design for GPGPUs", Hyunjun Chang, Jinchun Kim, Paul V. Gratz, Ki Hwan Yum, and Eun Jung Kim. The 52nd Annual ACM/EDAC/IEEE Design Automation Conference (DAC), June 2015. (PDF)
  • [MICRO '14] "B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors", David Kadjo, Jinchun Kim, Prabal Sharma, Reena Panda, Paul V. Gratz, and Daniel A. Jiménez. The 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), December 2014. Nominated for best paper (PDF)

Links

  • Google Scholar
  • ChampSim Github
  • The 2nd Cache Replacement Championship (CRC-2)
  • CAMSIN @ Texas A&M University
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