Towards the Ultimate Brain Computer –

Hardware Designs of Artificial & Spiking Neural Networks

Organizers & Presenters:

Jae-sun Seo (Arizona State University)

Bipin Rajendran (New Jersey Institute of Technology)


In recent years, machine learning algorithms and artificial neural networks (e.g. convolutional neural networks, deep neural networks) have found widespread use across a broad range of image, video, speech, and biomedical applications. For similar applications, there also has been a surge of interest in neuromorphic computing and spiking neural networks (e.g. TrueNorth chip from IBM), which more closely follow biological nervous systems. In this tutorial, we will present state-of-the-art research advances in hardware implementation of artificial neural networks and spiking neural networks, covering algorithms, architecture, circuits, and devices.

We will first introduce state-of-the-art algorithms for both artificial neural networks (ANNs) and spiking neural networks (SNNs). Then, we will present high-level architectural paradigms that are being pursued for accelerating these algorithms, such as tiled array of processing elements, cross-bars and other similar approaches, and highlight the trade-offs involved such as acceleration factor, fan-out, and connectivity patterns, area/power efficiency, etc. Subsequently, we will discuss recent demonstrations of ANN and SNN systems that employ scaled CMOS circuits. We will also discuss recent advances in using nanoscale devices, specifically emerging non-volatile memory devices for implementing neuronal and synaptic dynamics. Finally, we will present new hardware acceleration techniques and inter-disciplinary research directions for future energy-efficient cognitive systems.

Register for the tutorial here.

Tutorial Objectives

  • Provide attendees with understanding of both artificial and spiking neural networks
  • Learn state-of-the-art hardware implementations and design trade-offs for ANNs and SNNs
  • Understand how different hardware acceleration techniques (architecture, circuit, device) can affect area, performance, and power-efficiency of the target hardware system


  • Date & time: May 14 (Sunday), 2017, 1:30PM-3:30PM
  • Venue: William A. Egan Civic & Convention Center (555 W. Fifth Avenue, Anchorage, AK, USA)
  • Room at conf. venue: Parallel 5 (Room #4+7+8)