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LIST OF EXPERIMENTS
Video Explanation
Realization of logic functions using Universal gates | NAND & NOR | Malayalam |
This video explains simple method to realize any logic functions using universal gates (NAND & NOR gates)
Watch other digital electronics videos : https://www.youtube.com/playlist?list=PL5GLDcBhbkC97PtlEDpHV-a20p8wB2Ebs
Digital Electronics Lab | online simulation | Virtual Kit |V Lect 1simulation
Subject : Digital Electronics Lab
Topic : Online simulation & virtual Kit simulation
Realization of Half adder & Full Adder | Digital Electronics Lab VLect 2| Malayalam
Subject : Digital Electronics Lab
Topic : Half adder & Full adder realization
Realization of Half Sub-tractor & Full Sub-tractor| Digital Electronics Lab VLect 3| Malayalam
Subject : Digital Electronics Lab
Topic : Half adder & Full adder realization
Realization of Adder & Sub-tractor using universal gate (NAND) | DE Lab VLect 4 | Malayalam
Subject : Digital Electronics Lab
Topic : Half adder & Full adder realization using universal gate - NAND
Realization of SOP & POS function using K-Map | DE Lab VLect 5 | Malayalam
Subject : Digital Electronics Lab Topic : Half adder & Full adder realization using universal gate - NAND
Multiplexers, Logic design using 74151 IC | Simulation in multi-sim | DE Lab VLect 6 | Malayalam
Subject : Digital Electronics Lab
Topic : Multiplexers, Logic design using MUX IC
VERILOG
Familiarization of verilog programming | realization of basic gates | NOT & AND | Malayalam | vivado
This video explains the basic steps of verilog programming in vivado 2023 tool.
Lab manual : https://drive.google.com/file/d/19m03NnC6whdpXc_8aG80Tm517G5ir_7D/view?usp=sharing
Watch other digital electronics videos : https://www.youtube.com/playlist?list=PL5GLDcBhbkC97PtlEDpHV-a20p8wB2Ebs
Realizing Half adder & Full adder in Verilog | Structural & Dataflow | Malayalam | vivado
Contents
Lab manual : https://drive.google.com/file/d/1Won9Z5-tcp_5GZbHoilwgrmgHmcW6Yxe/view?usp=sharing
Watch other digital electronics videos : https://www.youtube.com/playlist?list=PL5GLDcBhbkC97PtlEDpHV-a20p8wB2Ebs
Realizing Multiplexer in Verilog | Structural | 8:1 MUX using 4:1 & 2:1 | Malayalam | vivado
Lab manual : https://drive.google.com/file/d/1wug5BkFOY12cwgV4FY0I-Uhe-v-safdc/view?usp=sharing
Watch other digital electronics videos : https://www.youtube.com/playlist?list=PL5GLDcBhbkC97PtlEDpHV-a20p8wB2Ebs
How to simulate Verilog in ModelSim: A beginner's guide | Model sim installation | Malayalam
This video give the step by step instructions for the installation steps of ModelSim software and simulation steps of Verilog programming in ModelSim
Contents
00:00 - Intro
00:15 - Downloading & Installation steps
01:41 - Simulating Verilog in ModelSim using test bench
09:09 - Simulating Verilog in ModelSim without test bench
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