About

I have designed and mass-produced semiconductors for 10 years since 2006.

In particular, I was in charge of hardware accelerator and full chip design in the field of display driver IC and touch screen controllers. 

And I have been working in the field of artificial intelligence since 2017.

I designed NPU architecture by the end of 2020 and worked on performance modeling of NLP model by the end of February 2022.

I am currently in charge of the chip design automation.

 Research Interests

• Chip Design Automation

• Optimizations

Education

• Mar. 2021 ~ Feb. 2023: MS student in Department of Computer Science and Engineering, Seoul National University (Advisor: Dr. Jaejin Lee)

• Mar. 1997 ~ Feb. 2006: BS student in School of Electrical Engineering and Computer Science, Kyungpook National University

Work Experiences

• Samsung Advanced Institute of Technology (2019~)

  • Machine Learning TU(2022~)

    • Chip design automation

      • Leader of Physical Design Activity

      • 1D/2D placement optimization project collaborating with DRAM Design Team

  • Green Supercomputer Architecture, Computing Platform Lab, System Center (2021~2022)

    • Analytic performance model design for NLP model and miniDFT

    • GPU power efficiency enhancement for HPL

  • Hyperscale Computing Platform, Computing Platform Lab, AI & S/W Center (2019~2020)

    • High utilization MAC architecture design and evaluation

    • High-level simulator design for the PPA analysis of the MAC architecture

    • Core architecture design for inference

    • Feasibility evaluation for enhanced lossless compression algorithm

    • Winograd algorithm feasibility evaluation

• Samsung Electronics Semiconductor Research Center (2014~2018)

  • Future Technology & Convergence Research Project TF (2018)

    • Future technology investigation and future project design

    • Feasibility evaluation for embedded FPGA

  • Deep Learning Platform Project in C-Lab (2017)

    • Team leader

    • 2D systolic array-based NPU using FPGA

    • New Lossless compression algorithm design

  • SW R&D Center (2014~2016)

    • Device driver design for in-house secure OS

    • Tool development for RTL design automation

• Samsung Electronics Display Solution Team (2006~2014)

  • LCD low power algorithm, IP design, FPGA evaluation, and mass production (Galaxy, iPhone, etc.)

  • OLED low power algorithm and IP design

  • Dynamic Capacitance Compensation IP design and mass production (Samsung digital camera)

  • World’s first Touch + Display Driver IC chip design

  • Touch Screen Controller full chip design, H/W accelerator IP design, and mass production (Samsung Galaxy S7~, OPPO and VIVO, etc.)

• Samsung S/W membership (2005)

  • Leader of SoC Team

  • 5-stage pipelined MIPS CPU design using FPGA

• Kyungpook National University (1997~2006)

  • Robot arm imitating hand movements (2004)

  • Sign language translator and chat system (2005)

Publications

• [Thesis] Hyungdal Kwon, Jaejin Lee, "Greedy-K: A New Local Optimization Algorithm for Solving 1D Circuit Placement Problems"

• Jinpyo Kim, Hyungdal Kwon, Jintaek Kang, Jihwan Park, Seungwook Lee, Jaejin Lee. "SnuHPL: high performance LINPACK for heterogeneous GPUs" Proceedings of the 36th ACM International Conference on Supercomputing (ICS), 2022

• Donghyun Kang, Jintaek Kang, Hyungdal Kwon, Hyunsik Park, Soonhoi Ha. "A Novel Convolutional Neural Network Accelerator That Enables Fully-Pipelined Execution of Layers" IEEE 37th International Conference on Computer Design (ICCD), 2019 

• Ki-Duk Kim, San-Ho Byun, Yoon-Kyung Choi, Jong-Hak Baek, Hwa-Hyun Cho, Jong-Kang Park, Hae-Yong Ahn, Chang-Ju Lee, Min-Soo Cho, Joo-Hyeon Lee, Sang-Woo Kim, Hyungdal Kwon, Yong-Yeob Choi, Chang-Ju Lee, Hwa-Hyun Cho, Jae-Suk Yu, Myunghee Lee. "A capacitive touch controller robust to display noise for ultrathin touch screen displays" IEEE International Solid-State Circuits Conference, 2012

• Hyoung-Rae Kim, Yoon-Kyung Choi, San-Ho Byun, Sang-Woo Kim, Kwang-Ho Choi, Hae-Yong Ahn, Jong-Kang Park, Dong-Yul Lee, Zhong-Yuan Wu, Hyung-Dal Kwon, Yong-Yeob Choi, Chang-Ju Lee, Hwa-Hyun Cho, Jae-Suk Yu. "A mobile-display-driver IC embedding a capacitive-touch-screen controller system" IEEE International Solid-State Circuits Conference - (ISSCC), 2010 

Patents (1st author)

• Method and apparatus with performance modeling (US20240061972A1)

• Method and apparatus with deep learning operations (US17/356771)

• Method and apparatus for performing deep learning operations (US17/102884)

• Method and apparatus with neural network data input and output control (US16/900007)

• Operating method of power optimization scheduler and computing apparatus including power optimization scheduler (US20210247838A1)

• Method and apparatus for performing deep learning operations (US17/168457)

• Memory device and method (US20210089610A1)

• Neural processing unit, neural processing system, and application system (US20200151549A1)

  • Electronic system including FPGA and operation method thereof (US11012075)

  • Method and device for controlling data input and output of fully connected network (US16/970859)

  • Touch screen controller for increasing data processing speed and touch system including the same (US10355737, US10141972)

  • Value adjustment methods, value adjustment signal processing apparatus, and image display systems using the same (US8791953)

• • 완전 연결 네트워크의 데이터 입력 및 출력을 제어하는 방법 및 장치 (P1020180020014)

  • 디스플레이 제어기 및 디스플레이 제어 방법 (KR20130084765A)

  • 디스플레이 패널 제어 장치 및 디스플레이 패널의 제어 프로그램이 기록된 컴퓨터로 판독 가 능한 기록 매체 (P1020170027638)

  • 부동산 정보 제공 및 공유 장치 (KR101692521)

  • 부동산 거래 가치 관리 장치 (KR101691305)

Awards and Honors

• 무한탐구상(Boundless Search for Breakthroughs Award, Jan. 2022)

• Green500 2nd/Top500 11th (Nov. 2021)

• Best Achievement Award (Jan. 2021)

• Prize of Business team leader of DDI (LCD low power algorithm IP) (2007)

• Joint Grand Prize at IDEC Design Competition. (MIPS CPU) (2005)